View UPD784046GCA1-XXX-3B9_3064303.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

mos integrated circuit pd784044(a), 784046(a) 16-bit single-chip microcontroller description the pd784046(a) is a model in the pd784046 subseries within the 78k/iv series. a stricter quality assurance program applies pd784046(a) compared to the pd784046 (standard model). (in terms of nec? quality grading, this is a ?pecial?grade product.) the pd784046(a) is provided with many peripheral hardware functions such as rom, ram, i/o port, 10-bit resolution a/d converter, timer, serial interface, and interrupt functions, in addition to a high-speed, high-performance cpu. the pd784046(a) is under development. moreover, a flash memory model, pd78f4046 note , that can operate on the same supply voltage as the mask rom model, and many development tools are under development. note use for functional evaluation only. the functions are described in detail in the following user? manuals. be sure to read these manuals when designing your system. pd784046 subseries user? manual - hardware : u11515e 78k/iv series user? manual - instruction : u10905e features higher reliability compared to the pd784044 and 784046 minimum instruction execution time : 160 ns (with 12.5-mhz internal clock) pd784044(a), 784046(a) 200 ns (with 10-mhz internal clock) pd784044(a1), (a2), 784046(a1), (a2) i/o port : 65 lines timer : 16-bit timer/counter 2 units 16-bit timer 3 units a/d converter : 10-bit resolution 16 channels serial interface uart/ioe (3-wire serial i/o) : 2 channels watchdog timer : 1 channel standby function halt/stop/idle mode supply voltage : v dd = 4.5 to 5.5 v application fields automotive appliances, etc. in this document, in addition to the pd784044(a) and pd784046(a), the pd784044(a1), 784044(a2) 784046(a1), and 784046(a2) are also explained. however, unless otherwise specified, the pd784046(a) is treated as the representative model throughout this document. the information in this document is subject to change without notice. document no. u13121ej1v1ds00 (1st edition) date published march 2001 n cp(k) printed in japan ? 1998 data sheet
pd784044(a), 784046(a) 2 data sheet u13121ej1v1ds ordering information part number package internal rom (bytes) internal ram (bytes) pd784044gc(a)- -3b9 80-pin plastic qfp (14 14 mm) 32 k 1024 pd784044gc(a1)- -3b9 80-pin plastic qfp (14 14 mm) 32 k 1024 pd784044gc(a2)- -3b9 80-pin plastic qfp (14 14 mm) 32 k 1024 pd784046gc(a)- -3b9 note 80-pin plastic qfp (14 14 mm) 64 k 2048 pd784046gc(a1)- -3b9 note 80-pin plastic qfp (14 14 mm) 64 k 2048 pd784046gc(a2)- -3b9 note 80-pin plastic qfp (14 14 mm) 64 k 2048 note under development remark indicates rom code suffix. quality grade special please refer to "quality grades on nec semiconductor devices" (document no. c11531e) published by nec corporation to know the specification of quality grade on the devices and its recommended applications. differences between pd784046 and pd784046(a) part number pd784044, 784046, 78f4046 pd784044(a), 784046(a) item quality grade standard special operating ambient temperature (t a ) ?0 to +70 ?c ?0 to +85 ?c operating frequency 8 to 32 mhz 8 to 25 mhz minimum instruction execution time 125 ns (with 16-mhz internal clock) 160 ns (with 12.5-mhz internal clock) dc characteristics v dd supply current differs. ac characteristics bus timing and serial operation differ. a/d converter characteristics conversion time and sampling time differ. differences between pd784046(a), 784046(a1) and 784046(a2) part number pd784046(a) pd784046(a1) pd784046(a2) item operating ambient temperature (t a ) ?0 to +85 ?c ?0 to +110 ?c ?0 to +125 ?c operating frequency 8 to 25 mhz 8 to 20 mhz minimum instruction execution time 160 ns (with 12.5-mhz 200 ns internal clock) (with 10-mhz internal clock) dc characteristics analog pin input leakage current, v dd supply current and data retention current differ. ac characteristics bus timing and serial operation differ. a/d converter characteristics av ref current and a/d converter data retention current differ. remark the differences between pd784044(a), 784044(a1) and 784044(a2) is the same as above table.
pd784044(a), 784046(a) 3 data sheet u13121ej1v1ds product development of 78k/iv series assp models standard models a/d, 16-bit timer, improved power management pd784026 pd784038y pd784216y pd784054 pd784046 pd784038 pd784216 pd784225y pd784218y pd784955 pd784908 pd78f4943 pd784915 pd784928y pd784928 for i 2 c bus for multimaster i 2 c bus internal 10-bit a/d for multimaster i 2 c bus 80 pins, rom correction added for multimaster i 2 c bus improved internal memory capacity, rom correction added for dc converter control internal iebus tm controller for cd-rom software servo control, internal analog circuit for vcr, improved timer for multimaster i 2 c bus improved functions of pd784915 improved internal memory capacity, pin compatible with pd784026 pd784225 pd784218 100 pins, i/o, improved internal memory capacity : under mass production : under development flash memory: 56 kb
pd784044(a), 784046(a) 4 data sheet u13121ej1v1ds function list item product pd784044(a) pd784046(a) number of basic 113 instructions (mnemonics) general-purpose register 8 bits 16 registers 8 banks, or 16 bits 8 registers 8 banks (memory mapping) minimum instruction 160 ns (with internal 12.5-mhz clock): pd784044(a), 784046(a) execution time 200 ns (with internal 10-mhz clock) : pd784044(a1), (a2), 784046(a1), (a2) internal rom 32k bytes 64 k bytes memory ram 1024 bytes 2048 bytes memory space 1m bytes with program/data combined i/o port total 65 pins input 17 pins i/o 48 pins pins with pins with 29 pins ancillary pull-up functions note resistors real-time output port 4 bits 1 timer/counter timer 0 : timer register 1, pulse output possible (16 bits) capture/compare register 4 toggle output set/reset output timer 1 : timer register 1, pulse output possible (16 bits) compare register 2 toggle output set/reset output timer/counter 2 : timer register 1, pulse output possible (16 bits) compare register 2 toggle output pwm/ppg output timer/counter 3 : timer register 1, pulse output possible (16 bits) compare register 2 toggle output pwm/ppg output timer 4 : timer register 1, pulse output possible (16 bits) compare register 2 read-time output (4 bits 1) a/d converter 10-bit resolution 16 channels serial interface uart/ioe (3-wire serial i/o): 2 channels (with baud rate generator) watchdog timer 1 channel interrupt hardware source 27 (internal: 23, external: 8 (internal/external: 4)) software source brk instruction, brkcs instruction, operand error non-maskable internal: 1, external: 1 maskable internal: 22, external: 7 (internal/external: 4) 4 levels of programmable priorities 3 processing formats: vectored interrupt/macro service/context switching bus sizing 8-bit/16-bit external data bus width selectable standby halt/stop/idle mode supply voltage v dd = 4.5 to 5.5 v package 80-pin plastic qfp (14 14 mm) note the pins with ancillary functions are included in the i/o pins.
pd784044(a), 784046(a) 5 data sheet u13121ej1v1ds contents 1. differences between pd784044(a) and 784046(a) ............................................................ 7 2. pin configuration (top view) ..................................................................................................... 8 3. system configuration example ...........................................................................................10 4. block diagram ............................................................................................................................. 11 5. pin functions ............................................................................................................................... .12 5.1 port pins ............................................................................................................................... ..................... 12 5.2 pins other than port pins ...................................................................................................................... 14 5.3 i/o circuits of pins and processing of unused pins .......................................................................... 16 6. cpu architecture .......................................................................................................................18 6.1 memory space ............................................................................................................................... ........... 18 6.2 cpu registers ............................................................................................................................... ............ 21 6.2.1 general-purpose registers ............................................................................................................. 21 6.2.2 control registers ............................................................................................................................. 22 6.2.3 special function registers (sfrs) .................................................................................................. 23 7. peripheral hardware functions ........................................................................................29 7.1 ports ............................................................................................................................... ............................ 29 7.2 clock generation circuit ......................................................................................................................... 30 7.3 real-time output port ............................................................................................................................. 32 7.4 timer/counter ............................................................................................................................... ............ 32 7.5 a/d converter ............................................................................................................................... ............ 35 7.6 serial interface ............................................................................................................................... ........... 36 7.6.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) ....................................................... 37 7.7 edge detection circuit ............................................................................................................................ 39 7.8 watchdog timer ............................................................................................................................... ......... 39 8. interrupt function ....................................................................................................................40 8.1 interrupt source ............................................................................................................................... ........ 40 8.2 vectored interrupt ............................................................................................................................... ..... 42 8.3 context switching ............................................................................................................................... ..... 43 8.4 macro service ............................................................................................................................... ............ 44 9. local bus interface .................................................................................................................47 9.1 memory expansion ............................................................................................................................... ... 48 9.2 memory space ............................................................................................................................... ........... 49 9.3 programmable wait ............................................................................................................................... ... 49 9.4 bus sizing function ............................................................................................................................... .. 49
pd784044(a), 784046(a) 6 data sheet u13121ej1v1ds 10. standby function .......................................................................................................................50 11. reset function ............................................................................................................................51 12. instruction set ...........................................................................................................................52 13. electrical specifications ......................................................................................................57 14. package drawing .......................................................................................................................80 15. recommended soldering conditions ................................................................................81 appendix a. development tools ................................................................................................82 appendix b. related documents ...............................................................................................85
pd784044(a), 784046(a) 7 data sheet u13121ej1v1ds 1. differences between pd784044(a) and 784046(a) the only difference between the pd784044(a) and pd784046(a) is the internal memory capacity. the differences are shown in table 1-1. table 1-1. differences between pd784044(a) and 784046(a) part number pd784044(a) pd784046(a) item internal rom 32k bytes 64k bytes (mask rom) (mask rom) internal ram 1024 bytes 2048 bytes
pd784044(a), 784046(a) 8 data sheet u13121ej1v1ds 2. pin configuration (top view) 80-pin plastic qfp (14 14 mm) pd784044gc(a)- -3b9, 784044gc(a1)- -3b9, 784044gc(a2)- -3b9 pd784046gc(a)- -3b9 note , 784046gc(a1)- -3b9 note , 784046gc(a2)- -3b9 note note under development caution directly connect the mode pin to v ss . p70/ani0 p71/ani1 p72/ani2 p73/ani3 p74/ani4 p75/ani5 p76/ani6 p77/ani7 av ref av dd v ss v dd p47/ad7 p46/ad6 p45/ad5 p44/ad4 p43/ad3 p42/ad2 p41/ad1 p40/ad0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 p22/intp1/to01 bwd p21/intp0/to00 mode p20/nmi v ss v dd p13/to31 p12/to30 p11/to21 p10/to20 p03/rtp3 p02/rtp2 p01/rtp1 p00/rtp0 p37/asck2/sck2 p36/txd2/so2 p35/rxd2/si2 p34/asck/sck1 p33/txd/so1 p50/ad8 p51/ad9 p52/ad10 p53/ad11 p54/ad12 p55/ad13 p56/ad14 p57/ad15 p60/a16 p61/a17 p62/a18 p63/a19 p90/rd p91/lwr p92/hwr p93/astb p94/wait p30/to10 p31/to11 p32/rxd/si1 p87/ani15 p86/ani14 p85/ani13 p84/ani12 p83/ani11 p82/ani10 p81/ani9 p80/ani8 av ss v dd x2 x1 v ss clkout p27/intp6/ti3 p26/intp5/ti2 p25/intp4 p24/intp3/to03 reset p23/intp2/to02 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40
pd784044(a), 784046(a) 9 data sheet u13121ej1v1ds a16-a19 : address bus ad0-ad15 : address/data bus ani0-ani15 : analog input asck, asck2 : asynchronous serial clock astb : address strobe av dd : analog power supply av ref : analog reference voltage av ss : analog ground bwd : bus width definition clkout : clock out hwr : high address write strobe intp0-intp6 : interrupt from peripherals lwr : low address write strobe mode : mode nmi : non-maskable interrupt p00-p03 : port0 p10-p13 : port1 p20-p27 : port2 p30-p37 : port3 p40-p47 : port4 p50-p57 : port5 p60-p63 : port6 p70-p77 : port7 p80-p87 : port8 p90-p94 : port9 rd : read strobe reset : reset rtp0-rtp3 : real-time port rxd, rxd2 : receive data sck1,sck2 : serial clock si1, si2 : serial input so1, so2 : serial output ti2, ti3 : timer input to00-to03, to10, to11, to20,to21,to30,to31 : timer output txd, txd2 : transmit data v dd : power supply v ss : ground wait : wait x1, x2 : crystal
pd784044(a), 784046(a) 10 data sheet u13121ej1v1ds 3. system configuration example (ac servo motor control) abs control unit pulse right front wheel speed left front wheel speed right rear wheel speed left rear wheel speed digital quantity brake sw parking sw neutral sw tcs cut sw, etc. input interface cpu general- purpose i/o timer unit interrupt controller serial i/o general- purpose i/o rom: 64 kb ram : 2 kb uart 10-bit a/d converter output interface solenoid drive circuit monitor circuit input interface external i/o interface subthrottle control display lamp analog quantity g sensor (front, rear) g sensor (left, right) throttle divergence rupture detection, etc. solenoid right front wheel left front wheel right rear wheel left rear wheel external tester display system microcomputer for monitor power unit battery voltage (12 v) pd784046(a)
pd784044(a), 784046(a) 11 data sheet u13121ej1v1ds 4. block diagram programmable interrupt controller intp0-intp6 nmi to00-to03 intp0-intp3 to10, to11 a/d converter av dd av ss av ref intp4 ani0-ani15 watchdog timer timer 4 (16 bits) timer 1 (16 bits) timer 0 (16 bits) 78k/iv cpu core rom ram bus i/f bwd ad0-ad15 a16-a19 rd lwr, hwr astb wait clkout reset mode x1 x2 system control p00-p03 port 0 port 1 port 2 port 3 port 4 port 5 port 6 port 7 port 8 port 9 p10-p12 p20 p21-p27 v dd v ss p30-p37 p40-p47 p50-p57 p60-p63 p70-p77 p80-p87 p90-p94 baud-rate generator uart/ioe1 baud-rate generator uart/ioe2 txd/so1 rxd/si1 asck/sck1 txd2/so2 rxd2/si2 asck2/sck2 timer/counter2 (16 bits) to20, to21 intp5/ti2 to30, to31 intp6/ti3 rtp0-rtp3 real-time output port timer/counter3 (16 bits) remark the internal rom and ram capacity differs depending on the products.
pd784044(a), 784046(a) 12 data sheet u13121ej1v1ds 5. pin functions 5.1 port pins (1/2) pin name i/o shared by: function p00-p03 i/o rtp0-rtp3 port 0 (p0): 4-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once via software. p10 i/o to20 port 1 (p1): p11 to21 4-bit i/o port p12 to30 can be set in input/output mode bit-wise. p13 to31 p20 input nmi port 2 (p2): input only p21 i/o intp0/to00 8-bit i/o port can be set in input/output mode p22 intp1/to01 bit-wise. p23 intp2/to02 p24 intp3/to03 p25 intp4 p26 intp5/ti2 p27 intp6/ti3 p30 i/o to10 port 3 (p3): p31 to11 8-bit i/o port p32 rxd/si1 can be set in input/output mode bit-wise. p33 txd/so1 p34 asck/sck1 p35 rxd2/si2 p36 txd2/so2 p37 asck2/sck2 p40-p47 i/o ad0-ad7 port 4 (p4): 8-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once via software. p50-p57 i/o ad8-ad15 port 5 (p5): 8-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once via software. p60-p63 i/o a16-a19 port 6 (p6): 4-bit i/o port can be set in input/output mode bit-wise. pins in input mode can all be connected to pull-up resistors at once via software.
pd784044(a), 784046(a) 13 data sheet u13121ej1v1ds 5.1 port pins (2/2) pin name i/o shared by: function p70-p77 input ani0-ani7 port 7 (p7): 8-bit input port p80-p87 input ani8-ani15 port 8 (p8): 8-bit input port p90 i/o rd port 9 (p9): p91 lwr 5-bit i/o port p92 hwr can be set in input/output mode bit-wise. p93 astb pins in input mode can all be connected to pull-up resistors at once p94 wait via software.
pd784044(a), 784046(a) 14 data sheet u13121ej1v1ds 5.2 pins other than port pins (1/2) pin name i/o shared by: function rtp0-rtp3 output p00-p03 real-time output nmi input p20 non-maskable interrupt request input intp0 p21/to00 external interrupt capture trigger signal of cc00 intp1 p22/to01 request input capture trigger signal of cc01 intp2 p23/to02 capture trigger signal of cc02 intp3 p24/to03 capture trigger signal of cc03 intp4 p25 conversion start trigger input of a/d converter intp5 p26/ti2 intp6 p27/ti3 to00 output p21/intp0 timer output from timer/counter to01 p22/intp1 to02 p23/intp2 to03 p24/intp3 to10 p30 to11 p31 to20 p10 to21 p11 to30 p12 to31 p13 ti2 input p26/intp5 external count clock input to timer/counter 2 ti3 p27/intp6 external count clock input to timer/counter 3 rxd input p32/si1 serial data input (uart0) rxd2 p35/si2 serial data input (uart2) txd output p33/so1 serial data output (uart0) txd2 p36/so2 serial data output (uart2) asck input p34/sck1 baud rate clock input (uart0) asck2 p37/sck2 baud rate clock input (uart2) si1 input p32/rxd serial data input (3-wire serial i/o1) si2 p35/rxd2 serial data input (3-wire serial i/o2) so1 output p33/txd serial data output (3-wire serial i/o1) so2 p36/txd2 serial data output (3-wire serial i/o2) sck1 i/o p34/asck serial clock input/output (3-wire serial i/o1) sck2 p37/asck2 serial clock input/output (3-wire serial i/o2) ad0-ad7 i/o p40-p47 lower multiplexed address/data bus when external memory is connected ad8-ad15 note i/o p50-p57 when 8-bit bus is specified higher address bus when external memory is connected when external 16-bit bus is specified higher multiplexed address/data bus when external memory is connected a16-a19 note output p60-p63 higher address bus when external memory is connected rd output p90 read strobe to external memory note the number of pins used as address bus pins differs depending on the external address space (refer to 9. local bus interface ).
pd784044(a), 784046(a) 15 data sheet u13121ej1v1ds 5.2 pins other than port pins (2/2) pin name i/o shared by: function lwr output p91 when external 8-bit bus is specified write strobe to external memory when external 16-bit bus is specified write strobe to external memory located at lower position hwr p92 write strobe to external memory located at higher position when external 16-bit bus is specified astb output p93 timing signal output to externally latch address information output from ad0 through ad15 pins to access external memory wait input p94 inserts wait. bwd input sets bus width. mode input directly connect this pin to v ss (this pin specifies test mode of ic). clkout output clock output. outputs low level during idle mode and stop mode. otherwise, always outputs f xx (oscillation frequency). x1 input connect crystal for system clock oscillation (clock can be also input to x1). x2 reset input chip reset ani0-ani7 input p70-p77 analog voltage input for a/d converter ani8-ani15 p80-p87 av ref reference voltage for a/d converter av dd positive power supply for a/d converter av ss gnd for a/d converter v dd positive power supply v ss gnd
pd784044(a), 784046(a) 16 data sheet u13121ej1v1ds 5.3 i/o circuits of pins and processing of unused pins table 5-1 shows the i/o circuit type of each pin and recommended processing of the unused pins. for the i/o circuit type, refer to figure 5-1 . table 5-1. i/o circuit type of each pin and recommended processing of unused pins pin name i/o circuit type i/o recommended connection of unused pins p00/rtp0-p03/rtp3 5-a i/o input: individually connect to v dd or v ss via resistor. p10-p12 5 output: leave unconnected. p11/to21 p12/to30 p13/to31 p20/nmi 2 input connect to v ss . p21/intp0/to00 8 i/o input: individually connect to v dd or v ss via resistor. p22/intp1/to01 output: leave unconnected. p23/intp2/to02 p24/intp3/to03 p25/intp4 p26/intp5/ti2 p27/intp6/ti3 p30/to10 5 p31/to11 p32/rxd/si1 p33/txd/so1 p34/asck/sck1 8 p35/rxd2/si2 5 p36/txd2/so2 p37/asck2/sck2 8 p40/ad0-p47/ad7 5-a p50/ad8-p57/ad15 p60/a16-p63/a19 p70/ani0-p77/ani7 9 input connect to v ss . p80/ani8-p87/ani15 p90/rd 5-a i/o input: individually connect to v dd or v ss via resistor. p91/lwr output: leave unconnected. p92/hwr p93/astb p94/wait mode 1 input directly connect to v ss . reset 2 clkout 3 output leave unconnected. av ref connect to v ss . av ss av dd connect to v dd . remark the circuit type numbers are serial in the 78k series but are not always so with some models (because some models are not provided with particular circuits).
pd784044(a), 784046(a) 17 data sheet u13121ej1v1ds figure 5-1. i/o circuits of pins type 2 schmitt trigger input with hysteresis characteristics type 1 p-ch in v dd n-ch in type 3 type 5 data output disable p-ch in/out v dd n-ch input enable type 5-a data output disable p-ch in/out v dd n-ch input enable p-ch v dd pullup enable type 8 data output disable p-ch in/out v dd n-ch in comparator + v ref (threshold voltage) p-ch n-ch input enable type 9 p-ch out v dd n-ch
pd784044(a), 784046(a) 18 data sheet u13121ej1v1ds 6. cpu architecture 6.1 memory space a 1m-byte memory space can be accessed. the mapping of the internal data area (special function registers and internal ram) can be selected by using the location instruction. the location instruction must be always executed after the reset signal has been deasserted, and must not be used more than once. (1) when location 0 instruction is executed internal memory the internal data area and internal rom area are as follows: product name internal data area internal rom area pd784044(a) 0fb00h-0ffffh 00000h-07fffh pd784046(a) 0f700h-0ffffh 00000h-0f5ffh caution 0f600h to 0ffffh of the on-chip rom (00000h to 0ffffh) of the pd784046(a) cannot be used as rom in execution of the location 0 instruction (refer to figure 6-2). external memory the external memory is accessed in the external memory expansion mode. (2) when location 0fh instruction is executed internal memory the internal data area and internal rom area are as follows: product name internal data area internal rom area pd784044(a) ffb00h-fffffh 00000h-07fffh pd784046(a) ff700h-fffffh 00000h-0ffffh external memory the external memory is accessed in the external memory expansion mode.
pd784044(a), 784046(a) 19 data sheet u13121ej1v1ds figure 6-1. pd784044(a) memory map notes 1. accessed in the external memory expansion mode. 2. base area or entry area by reset or interrupt. the internal ram is not reset. external memory note 1 (960k bytes) special function registers (sfrs) note 1 (256 bytes) internal memory (1k bytes) cannot be used (1280 bytes) internal rom (32k bytes) h general-purpose registers (128 bytes) macro service control word area (50 bytes) data area (512 bytes) program/data area (512 bytes) program/data area (32k bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) when location 0 instruction is executed cannot be used (1280 bytes) external memory note 1 (1013248 bytes) internal rom (32k bytes) when location 0fh instruction is executed special function registers (sfr s ) note 1 (256 bytes) internal ram (1k bytes) note 2 main ram peripheral ram f f f f f h h h h h h 0 f f 0 0 f 0 f d d 0 f 0 f f f f e 0 f f f f f 1 0 0 0 0 0 h h 0 f 0 f b a f f 0 0 h h 0 f 0 f 6 5 f f 0 0 h h 0 f 0 f 0 f 8 7 0 0 h 0 0 0 0 0 external memory note 1 (30208 bytes) h f f e f 0 h h 0 f 8 7 e e f f 0 0 h h 7 6 3 0 e e f f 0 0 h h 0 f 0 f d c f f 0 0 h 0 0 b f 0 h f f f 7 0 h h 0 f 0 f 0 f 1 0 0 0 h h 0 f 0 f 8 7 0 0 0 0 h h 0 f 8 7 0 0 0 0 0 0 h 0 0 0 0 0 h f f e f f h h 0 f 8 7 e e f f f f h h 7 6 3 0 e e f f f f h h 0 f 0 f d c f f f f h 0 0 b f f h h h h f f 0 0 f d d 0 f f f f f f f f f f f f h h 0 f 0 f 6 5 f f f f h h 0 f 0 f 0 f 8 7 0 0 h 0 0 0 0 0 h h 0 f 0 f 0 f 0 f 1 0 h h 0 f 0 f b a f f f f note 2 h h 0 f 4 3 0 0 0 0 0 0 h f f e f f
pd784044(a), 784046(a) 20 data sheet u13121ej1v1ds figure 6-2. pd784046(a) memory map external memory note 1 (960k bytes) note 1 internal ram (2k bytes) internal rom (62976 bytes) general-purpose registers (128 bytes) macro service control word area (50 bytes) data area (512 bytes) program/data area (1536 bytes) callf entry area (2k bytes) callt table area (64 bytes) vector table area (64 bytes) when location 0 instruction is executed cannot be used (256 bytes) external memory note 1 (980480 bytes) internal rom (64k bytes) special function registers (sfrs) note 1 (256 bytes) internal ram (2k bytes) special function registers (sfrs) (256 bytes) cannot be used (256 bytes) program/data area note 3 note 2 peripheral ram main ram h 0 0 0 0 0 h f f 5 f 0 h 0 0 6 f 0 h f f 6 f 0 h f f f f f h f f e f 0 h 0 0 7 f 0 h 0 0 f f 0 h 0 d f f 0 h f d f f 0 h f f f f 0 h 0 0 0 0 1 note 4 h f f e f 0 h 0 8 e f 0 h f 7 e f 0 h 7 3 e f 0 h 6 0 e f 0 h 0 0 d f 0 h 0 0 7 f 0 h f f c f 0 h 0 0 5 f 0 h 0 0 0 0 0 h f 3 0 0 0 h 0 4 0 0 0 h f 7 0 0 0 h 0 8 0 0 0 h f f 7 0 0 h 0 0 0 1 0 h f f f 0 0 h 0 0 0 1 0 h 0 0 0 0 0 h f f f f 0 h 0 0 0 0 1 h f f 5 f f h 0 0 6 f f h f f 6 f f h 0 0 7 f f h f f f f f h 0 0 f f f h 0 d f f f h f d f f f h f f e f f h f f e f f h 0 8 e f f h f 7 e f f h 7 3 e f f h 6 0 e f f h 0 0 d f f h f f c f f h 0 0 7 f f h f f f f 0 note 4 when location 0fh instruction is executed notes 1. accessed in the external memory expansion mode. 2. 2560 bytes in this area can be used as inernal rom only when the location 0fh instruction is executed. 3. when the location 0 instruction is executed: 62976 bytes when the location 0fh instruction is executed: 65536 bytes 4. base area or entry area by reset or interrupt. the internal ram is not reset.
pd784044(a), 784046(a) 21 data sheet u13121ej1v1ds 6.2 cpu registers 6.2.1 general-purpose registers sixteen 8-bit general-purpose registers are provided. two 8-bit general-purpose registers can be used in pairs as a 16-bit general-purpose register. of the 16-bit registers, four can be used with an 8-bit register for address expansion as 24-bit address specification registers. eight banks of register sets are available which can be selected by software or context switching function. the general-purpose registers except the v, u, t, and w registers for address expansion are mapped to the internal ram. figure 6-3. general-purpose register format caution r4, r5, r6, r7, rp2, and rp3 can be used as x, a, c, b, ax, and bc registers, respectively, by setting the rss bit of the psw to 1. however, use this function only when using a 78k/iii series program. v u t w a(r1) b(r3) r5 r7 r9 r11 d(r13) h(r15) r8 r10 e(r12) l(r14) vvp(rg4) uup(rg5) tde(rg6) whl(rg7) x(r0) c(r2) r4 r6 vp(rp4) up(rp5) de(rp6) hl(rp7) ax(rp0) bc(rp1) rp2 rp3 ( ): absolute name 8 banks
pd784044(a), 784046(a) 22 data sheet u13121ej1v1ds 6.2.2 control registers (1) program counter (pc) this is a 20-bit program counter. its contents are automatically updated as the program is executed. figure 6-4. program counter (pc) format (2) program status word (psw) this register retains the status of the cpu and its contents are automatically updated as the program is executed. figure 6-5. program status word (psw) format note this flag is provided so that the pd784046(a) maintains compatibility with the 78k/iii series. be sure to clear this flag to 0 when using 78k/iii series software. (3) stack pointer (sp) this is a 24-bit pointer that holds the first address of the stack. be sure to write 0 to the high-order 4 bits of this pointer. figure 6-6. stack pointer (sp) format 19 0 pc pswh uf rbs2 rbs1 rbs0 15 14 13 12 11 9 10 8 psw pswl s z rss note ac ie p/v 0 cy 76543 1 20 sp 0 23 0 0 00 20
pd784044(a), 784046(a) 23 data sheet u13121ej1v1ds 6.2.3 special function registers (sfrs) the special function registers are registers to which special functions are assigned, and include the mode registers and control registers of the internal peripheral hardware. these registers are mapped to a 256-byte space of addresses 0ff00h through 0ffffh note . note when the location 0 instruction is executed. fff00h through fffffh when the location 0fh instruction is executed. caution do not access an address in this area to which no sfr is allocated. if an address to which no sfr is allocated is accessed by mistake, the pd784046(a) may be deadlocked. the deadlock status can be cleared only by inputting the reset signal. table 6-1 lists the special function registers. the meanings of the symbols in this table are as follows: symbol ................................. symbol indicating an sfr. these symbols are reserved for an nec s assembler (ra78k4). with a c compiler (cc78k4), they can be used as sfr variables by using the #pragma sfr directive. r/w ...................................... indicates whether the corresponding sfr can be read/written. r/w : read/write r : read only w : write only bit units for manipulation .... indicates bit units in which the corresponding sfr can be manipulated. sfrs that can be manipulated in 16-bit units can be written as operand sfrp. specify the even addresses of these sfrs when specifying an address. sfrs that can be manipulated bit-wise can be written in bit manipulation instructions. on reset ............................... indicates the status of each register when the reset signal is input.
pd784044(a), 784046(a) 24 data sheet u13121ej1v1ds table 6-1. special function register list (1/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff00h port 0 p0 r/w undefined 0ff01h port 1 p1 0ff02h port 2 p2 note 2 0ff03h port 3 p3 r/w 0ff04h port 4 p4 0ff05h port 5 p5 0ff06h port 6 p6 0ff07h port 7 p7 r 0ff08h port 8 p8 0ff09h port 9 p9 r/w 0ff0eh port 0 buffer register p0l 0ff10h timer register 0 tm0 r 0000h 0ff11h 0ff12h capture/compare register 00 cc00 r/w undefined 0ff13h 0ff14h capture/compare register 01 cc01 0ff15h 0ff16h capture/compare register 02 cc02 0ff17h 0ff18h capture/compare register 03 cc03 0ff19h 0ff1ah timer register 1 tm1 r 0000h 0ff1bh 0ff1ch compare register 10 cm10 r/w undefined 0ff1dh 0ff1eh compare register 11 cm11 0ff1fh 0ff20h port 0 mode register pm0 ffh 0ff21h port 1 mode register pm1 0ff22h port 2 mode register pm2 note 3 0ff23h port 3 mode register pm3 0ff24h port 4 mode register pm4 0ff25h port 5 mode register pm5 0ff26h port 6 mode register pm6 0ff29h port 9 mode register pm9 0ff2eh real-time output port control register rtpc 00h 0ff2fh port read control register prdc notes 1. when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. bit 0 of p2 can only be read. bit 1 can be read/written. 3. bit 0 of pm2 is fixed to 1 by hardware.
pd784044(a), 784046(a) 25 data sheet u13121ej1v1ds table 6-1. special function register list (2/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff30h timer unit mode register 0 tum0 r/w 00h 0ff31h timer mode control register tmc 0ff32h timer output control register 0 toc0 0ff33h timer output control register 1 toc1 0ff34h timer unit mode register 2 tum2 0ff35h timer mode control register 2 tmc2 0ff36h timer output control register 2 toc2 0ff37h timer mode control register 4 tmc4 0ff38h prescaler mode register prm 0ff39h prescaler mode register 2 prm2 0ff3ah prescaler mode register 4 prm4 0ff3bh noise protection control register npc 0ff3ch external interrupt mode register 0 intm0 0ff3dh external interrupt mode register 1 intm1 0ff3eh interrupt valid edge flag register 1 ief1 undefined 0ff3fh interrupt valid edge flag register 2 ief2 0ff41h port 1 mode control register pmc1 00h 0ff42h port 2 mode control register pmc2 note 2 0ff43h port 3 mode control register pmc3 0ff49h port 9 mode control register pmc9 0ff4eh pull-up resistor option register l puol 0ff4fh pull-up resistor option register h puoh 0ff50h timer register 2 tm2 r 0000h 0ff51h 0ff52h compare register 20 cm20 r/w undefined 0ff53h 0ff54h compare register 21 cm21 0ff55h 0ff56h timer register 3 tm3 r 0000h 0ff57h 0ff58h compare register 30 cm30 r/w undefined 0ff59h 0ff5ah compare register 31 cm31 0ff5bh 0ff60h timer register 4 tm4 r 0000h 0ff61h notes 1. when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. bits 0, and 5 through 7 of pmc2 are fixed to 0 by hardware.
pd784044(a), 784046(a) 26 data sheet u13121ej1v1ds table 6-1. special function register list (3/5) address note special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff62h compare register 40 cm40 r/w undefined 0ff63h 0ff64h compare register 41 cm41 0ff65h 0ff6eh a/d converter mode register adm 00h 0ff70h a/d conversion result register 0 adcr0 r undefined 0ff71h 0ff71h a/d conversion result register 0h adcr0h 0ff72h a/d conversion result register 1 adcr1 0ff73h 0ff73h a/d conversion result register 1h adcr1h 0ff74h a/d conversion result register 2 adcr2 0ff75h 0ff75h a/d conversion result register 2h adcr2h 0ff76h a/d conversion result register 3 adcr3 0ff77h 0ff77h a/d conversion result register 3h adcr3h 0ff78h a/d conversion result register 4 adcr4 0ff79h 0ff79h a/d conversion result register 4h adcr4h 0ff7ah a/d conversion result register 5 adcr5 undefined 0ff7bh 0ff7bh a/d conversion result register 5h adcr5h 0ff7ch a/d conversion result register 6 adcr6 0ff7dh 0ff7dh a/d conversion result register 6h adcr6h 0ff7eh a/d conversion result register 7 adcr7 0ff7fh 0ff7fh a/d conversion result register 7h adcr7h 0ff84h clocked serial interface mode register 1 csim1 r/w 00h 0ff85h clocked serial interface mode register 2 csim2 0ff88h asynchronous serial interface mode register asim 0ff89h asynchronous serial interface mode register 2 asim2 0ff8ah asynchronous serial interface status register asis r 0ff8bh asynchronous serial interface status register 2 asis2 note when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed.
pd784044(a), 784046(a) 27 data sheet u13121ej1v1ds table 6-1. special function register list (4/5) address note 1 special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ff8ch serial receive buffer: uart0 rxb r undefined serial transmit shift register: uart0 txs w serial shift register: ioe1 sio1 r/w 0ff8dh serial receive buffer: uart2 rxb2 r serial transmit shift register: uart2 txs2 w serial shift register: ioe2 sio2 r/w 0ff90h baud rate generator control register brgc 00h 0ff91h baud rate generator control register 2 brgc2 0ffa8h in-service priority register ispr r 0ffaah interrupt mode control register imc r/w 80h 0ffach interrupt mask register 0l mk0l ffh 0ffach interrupt mask register 0 mk0 ffffh 0ffadh 0ffadh interrupt mask register 0h mk0h ffh 0ffaeh interrupt mask register 1l mk1l 0ffaeh interrupt mask register 1 mk1 ffffh 0ffafh 0ffafh interrupt mask register 1h mk1h ffh 0ffc0h standby control register note 2 stbc 30h 0ffc2h watchdog timer mode register note 2 wdm 00h 0ffc4h memory expansion mode register mm 20h 0ffc7h programmable wait control register 1 pwc1 aah 0ffc8h programmable wait control register 2 pwc2 aaaah 0ffc9h 0ffcah bus width specification register bw note 3 0ffcbh 0ffcfh oscillation stabilization time specification register osts 00h 0ffd0h- external sfr area undefined 0ffdfh 0ffe0h interrupt control register (intov0) ovic0 43h 0ffe1h interrupt control register (intov1) ovic1 0ffe2h interrupt control register (intov4) ovic4 0ffe3h interrupt control register (intp0) pic0 0ffe4h interrupt control register (intp1) pic1 0ffe5h interrupt control register (intp2) pic2 notes 1. when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed. 2. these registers can be written only by using dedicated instructions mov stbc, #byte and mov wdm, #byte, and cannot be written by any other instructions. 3. the value of this register on reset differs depending on the setting of the bwd pin. bwd = 0: 0000h bwd = 1: 00ffh
pd784044(a), 784046(a) 28 data sheet u13121ej1v1ds table 6-1. special function register list (5/5) address note special function register (sfr) name symbol r/w bit units for manipulation on reset 1 bit 8 bits 16 bits 0ffe6h interrupt control register (intp3) pic3 r/w 43h 0ffe7h interrupt control register (intp4) pic4 0ffe8h interrupt control register (intp5) pic5 0ffe9h interrupt control register (intp6) pic6 0ffeah interrupt control register (intcm10) cmic10 0ffebh interrupt control register (intcm11) cmic11 0ffech interrupt control register (intcm20) cmic20 0ffedh interrupt control register (intcm21) cmic21 0ffeeh interrupt control register (intcm30) cmic30 0ffefh interrupt control register (intcm31) cmic31 0fff0h interrupt control register (intcm40) cmic40 0fff1h interrupt control register (intcm41) cmic41 0fff2h interrupt control register (intser) seric 0fff3h interrupt control register (intsr) sric interrupt control register (intcsi1) csiic1 0fff4h interrupt control register (intst) stic 0fff5h interrupt control register (intser2) seric2 0fff6h interrupt control register (intsr2) sric2 interrupt control register (intcsi2) csiic2 0fff7h interrupt control register (intst2) stic2 0fff8h interrupt control register (intad) adic note when the location 0 instruction is executed. add f0000h to this value when the location 0fh instruction is executed.
pd784044(a), 784046(a) 29 data sheet u13121ej1v1ds 7. peripheral hardware functions 7.1 ports the pd784046(a) has the ports shown in figure 7-1. these ports can be used for various control operations. the function of each port is shown in table 7-1. ports 0, 4 through 6, and 9 can be connected to an internal pull-up resistor via software when they are set in the input mode. figure 7-1. port configuration port 0 port 1 port 2 port 3 port 4 port 5 port 6 p00 p03 p10 p13 p20 p27 p30 p37 p40 p47 p50 p57 p60 p63 p70-p77 8 port 7 port 9 p80-p87 8 port 8 p90 p94
pd784044(a), 784046(a) 30 data sheet u13121ej1v1ds table 7-1. port function port name pin name function specification of pull-up resistor by software port 0 p00-p03 can be set in input or output mode bit-wise. all pins in input mode port 1 p10-p13 port 2 p20-p27 can be set in input or output mode bit-wise (however, p20 is input-only). port 3 p30-p37 can be set in input or output mode bit-wise. port 4 p40-p47 all pins in input mode port 5 p50-p57 port 6 p60-p63 port 7 p70-p77 input port port 8 p80-p87 port 9 p90-p94 can be set in input or output mode bit-wise. all pins in input mode 7.2 clock generation circuit the clock generation circuit generates and controls the internal system clock (clk) to be supplied to the cpu. figure 7-2 shows the configuration of this circuit. figure 7-2. block diagram of clock generation circuit remark f xx : crystal/ceramic oscillation frequency f x : external clock frequency f clk : internal system clock frequency internal system clock (clk) clock generation circuit f xx or f x f clk x2 x1 divider 1/2
pd784044(a), 784046(a) 31 data sheet u13121ej1v1ds figure 7-3. example of using oscillation circuit (1) crystal/ceramic oscillation caution when using the clock oscillation circuit, wire the portion enclosed by the dotted line in the above figure as follows to avoid adverse effects of wiring capacitance. keep the wiring length as short as possible. do not cross the wiring with other signal lines. do not route the wiring in the vicinity of lines through which a high alternating current flows. always keep the ground point of the capacitor of the oscillation circuit at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not extract signals from the oscillation circuit. (2) external clock input (a) extc bit of osts = 1 (b) extc bit of osts = 0 pd784046(a) v ss x1 x2 pd74hc04, etc. pd784046(a) x1 x2 pd784046(a) x1 x2 leave unconnected
pd784044(a), 784046(a) 32 data sheet u13121ej1v1ds 7.3 real-time output port the real-time output port outputs the data stored in the buffer in synchronization with a match interrupt of timer 4. this allows jitter-less pulse output to be obtained. therefore, it is best suited to applications that output patterns at given intervals (such as stepping motor open loop control,etc.). as shown in figure 7-4, port 0 and the port 0 buffer register form the core of configuration. figure 7-4. block diagram of real-time output port 7.4 timer/counter the pd784046(a) contains two 16-bit timer/counter units and three 16-bit timer units. these units support a total of 15 interrupt requests, which enable them to function as 15-channel timers. table 7-2. timer/counter function name timer 0 timer 1 timer/ timer/ timer 4 item counter2 counter 3 operating mode interval timer 4ch 2ch 2ch 2ch 2ch external event counter function timer output 4ch 2ch 2ch 2ch toggle output set/reset output pwm/ppg output real-time output overflow interrupt number of interrupt requests 53223 internal bus 8 real time output port control register (rtpc) output trigger control circuit intcm40 (from timer 4) 4 port 0 buffer register (p0l) 4 output latch (p0) rtp0 rtp3 rtp2 rtp1 4
pd784044(a), 784046(a) 33 data sheet u13121ej1v1ds figure 7-5. block diagram of timer/counter (1/2) timer 0 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 timer 1 prescaler: f clk /8, f clk /16, f clk /32, f clk /64, f clk /128 prescaler timer register 0 (tm0) f clk intp0 intp1 intp2 intp3 intov0 edge detection capter/compare register 00 (cc00) intp0 intcc00 coinci- dence to00 pulse output control edge detection capter/compare register 01 (cc01) intp1 intcc01 coinci- dence to01 edge detection capter/compare register 02 (cc02) intp2 intcc02 coinci- dence to02 pulse output control edge detection capter/compare register 03 (cc03) intp3 intcc03 coinci- dence to03 f clk prescaler timer register 1 (tm1) compare register 10 (cm10) intcm10 coinci- dence to10 pulse output control compare register 11 (cm11) intcm11 coinci- dence to11 clear control intov1
pd784044(a), 784046(a) 34 data sheet u13121ej1v1ds figure 7-5. block diagram of timer/counter (2/2) timer/counter 2 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 f clk prescaler timer register 4 (tm4) compare register 40 (cm40) coinci- dence to real-time output port compare register 41 (cm41) coinci- dence intcm41 clear control intov4 intcm40 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 timer 4 prescaler: f clk /4, f clk /8, f clk /16, f clk /32, f clk /64 timer/counter 3 f clk prescaler timer register 2 (tm2) compare register 20 (cm20) intcm20 coinci- dence to20 pulse output control compare register 21 (cm21) intcm21 to21 clear control selector ti2/intp5 edge detection intp5 coinci- dence f clk prescaler timer register 3 (tm3) compare register 30 (cm30) intcm30 to30 pulse output control compare register 31 (cm31) intcm31 coinci- dence to31 clear control selector ti3/intp6 edge detection intp6 coinci- dence
pd784044(a), 784046(a) 35 data sheet u13121ej1v1ds 7.5 a/d converter the pd784046(a) has an analog-to-digital (a/d) converter with 16 multiplexed analog input pins (ani0 through ani15). this converter is of successive approximation type. the result of conversion is stored to and retained in 10-bit a/d conversion result registers (adcr0-adcr7). therefore, high-speed, high-accuracy conversion can be performed (conversion time: about 13.5 s: f clk = 12.5 mhz). the a/d conversion operation can be started in the following modes: hardware start : conversion is started by trigger input (intp4). software start : conversion is started by setting a bit of the a/d converter mode register (adm). the a/d converter operates in the following modes: scan mode : sequentially selects two or more analog input pins to obtain data to be converted from all the pins. select mode : selects only one analog input pin to obtain successive conversion values. the above modes and stopping the conversion are specified by adm. when the result of conversion is transferred to adcrn (n = 0-7), interrupt request intad is generated. by using this interrupt request and by using macro service, the converted value can be successively transferred to memory. figure 7-6. block diagram of a/d converter internal bus input selector ani0 ani1 ani2 ani3 ani4 ani5 ani6 ani7 input selector ani8 ani9 ani10 ani11 ani12 ani13 ani14 ani15 sample & hold circuit successive approximation register (sar) voltage comparator edge detection circuit intp4 control circuit conversion trigger intad 10 trigger enable a/d converter mode register (adm) series resistor string r/2 r r/2 av ref av ss 8 10 adcr0 adcr1 adcr2 adcr3 adcr4 adcr5 adcr6 adcr7 a/d conversion result register tap selector
pd784044(a), 784046(a) 36 data sheet u13121ej1v1ds 7.6 serial interface the pd784046(a) is provided with two independent serial interface channels. asynchronous serial interface (uart)/3-wire serial i/o (ioe) 2 by using these serial interface channels, communication with an external device and local communication within a system can be performed at the same time (refer to figure 7-7 ). figure 7-7. example of serial interface rxd txd port rs-232c driver/ receiver (uart) pd784046(a) master so2 si2 sck2 intpn port si so sck port int note slave (3-wire serial i/o) note handshake line
pd784044(a), 784046(a) 37 data sheet u13121ej1v1ds 7.6.1 asynchronous serial interface/3-wire serial i/o (uart/ioe) two serial interface channels from which asynchronous serial interface mode and three-wire serial i/o mode can be selected are provided. (1) asynchronous serial interface mode in this mode, 1-byte data following a start bit is transferred or received. the internal baud rate generator allows communication in a wide range of baud rates. the clock input to the asck pin can also be divided to define a baud rate. the baud rate generator can also set a baud rate conforming to the midi standard (31.25 kbps). figure 7-8. block diagram in asynchronous serial interface mode remark f clk : internal system clock n = 0 to 11 m = 16 to 30 internal bus receive buffer rxb, rxb2 receive shift register transmit shift register intst, intst2 txs, txs2 transmit control parity append receive control parity check intsr, intsr2 intser, intser2 rxd, rxd2 txd, txd2 1/2m 1/2m 1/2 n+1 f clk asck, asck2 baud rate generator selector
pd784044(a), 784046(a) 38 data sheet u13121ej1v1ds (2) 3-wire serial i/o mode this mode is to start transmission when the master device makes a serial clock active and to communicate 1-byte data in synchronization with this clock. the interface in this mode communicates with devices that have conventional clocked serial interface. basically, communication is performed by using three lines: serial clock (sck) and two serial data (si and so) lines. to connect two or more devices, a handshake line is necessary. figure 7-9. block diagram in 3-wire serial i/o mode remark f clk : internal system clock n = 0 to 11 m = 1, 16 to 30 internal bus direction control circuit shift register sio1, sio2 output latch serial clock counter interrupt generation circuit intcsi1, intcsi2 serial clock control circuit 1/2m 1/2 n+1 f clk si1, si2 so1, so2 sck1, sck2 selector
pd784044(a), 784046(a) 39 data sheet u13121ej1v1ds 7.7 edge detection circuit the interrupt input pins (nmi and intp0 through intp6) input not only interrupt requests but also trigger signals of the internal hardware. because all the interrupts and internal hardware operate by detecting specific edges of the input signals, a function to detect edges is provided. in addition, a noise rejection function is also provided to prevent detection of a wrong edge due to noise. pin detectable edge noise rejected by: nmi either rising or falling edge analog delay intp0-intp6 either rising or falling edge, or both edges clock sampling note note a sampling clock can be selected. 7.8 watchdog timer a watchdog timer is provided to detect a hang-up of the cpu. this watchdog timer generates a non-maskable interrupt unless it is cleared by software within a specified interval time. once the watchdog timer has been enable to operate, its operation cannot be stopped by software. moreover, it can be specified whether the interrupt by the watchdog timer or the interrupt from the nmi pin takes precedence. figure 7-10. block diagram of watchdog timer watchdog timer (8 bits) overflow wdt clr f clk intwdt f clk /2 9 f clk /2 11 f clk /2 12 f clk /2 13 divider selector
pd784044(a), 784046(a) 40 data sheet u13121ej1v1ds 8. interrupt function the three types of interrupt processing shown in table 8-1 can be selected. table 8-1. interrupt request processing processing mode processed by: processing contents of pc and psw vectored interrupt software branches to and executes processing routine saves and restores to/from (any processing contents). stack. context switching automatically selects register bank, and branches saves or restores to/from to and executes processing routine (any fixed area in register bank. processing contents). macro service firmware executes data transfer between memory and i/o retained (any processing contents). 8.1 interrupt source as interrupt sources, twenty-seven sources listed in table 8-2, brk instruction execution, and operand error are available. four priority levels of interrupt processing can be selected, so that nesting during interrupt processing and the levels of interrupt requests that are generated at the same time can be controlled. however, nesting always advances with macro service (i.e., nesting is not kept pending). the default priority is the priority (fixed) of the processing for the interrupt requests that have occurred at the same time and have the same priority level (refer to table 8-2 ).
pd784044(a), 784046(a) 41 data sheet u13121ej1v1ds table 8-2. interrupt sources type default source internal/ macro priority name trigger external service software brk instruction execution of instruction brkcs instruction operand error if result of exclusive or of operands byte and byte is not ffh when mov stbc, #byte, mov wdm, #byte, or location instruction is executed non- nmi detection of pin input edge external maskable intwdt overflow of watchdog timer internal maskable 0 (highest) intov0 overflow of timer 0 1 intov1 overflow of timer 1 2 intov4 overflow of timer 4 3 intp0 detection of pin input edge (cc00 capture trigger) external intcc00 generation of tm0-cc00 coincidence signal internal 4 intp1 detection of pin input edge (cc01 capture trigger) external intcc01 generation of tm0-cc01 coincidence signal internal 5 intp2 detection of pin input edge (cc02 capture trigger) external intcc02 generation of tm0-cc02 coincidence signal internal 6 intp3 detection of pin input edge (cc03 capture trigger) external intcc03 generation of tm0-cc03 coincidence signal internal 7 intp4 detection of pin input edge external (a/d converter conversion start trigger) 8 intp5 detection of pin input edge (tm2 event counter input) 9 intp6 detection of pin input edge (tm3 event counter input) 10 intcm10 generation of tm1-cm10 coincidence signal internal 11 intcm11 generation of tm1-cm11 coincidence signal 12 intcm20 generation of tm2-cm20 coincidence signal 13 intcm21 generation of tm2-cm21 coincidence signal 14 intcm30 generation of tm3-cm30 coincidence signal 15 intcm31 generation of tm3-cm31 coincidence signal 16 intcm40 generation of tm4-cm40 coincidence signal 17 intcm41 generation of tm4-cm41 coincidence signal 18 intser occurrence of uart0 reception error 19 intsr end of uart0 reception intcsi1 end of 3-wire serial i/o1 transfer 20 intst end of uart0 transfer 21 intser2 occurrence of uart2 reception error 22 intsr2 end of uart2 reception intcsi2 end of 3-wire serial i/o2 transfer 23 intst2 end of uart2 transfer 24 (lowest) intad end of a/d converter conversion (transfer to adcr)
pd784044(a), 784046(a) 42 data sheet u13121ej1v1ds 8.2 vectored interrupt execution branches to a processing routine by using the memory contents of the vector table address corresponding to an interrupt source as the branch destination address. the following operations are performed so that the cpu processes the interrupt: on branch : saves status of cpu (contents of pc and psw) to stack on returning : restores status of cpu from stack execution is returned from the processing routine to the main routine by the reti instruction. the branch destination address must be in a range of 0 to ffffh. table 8-3. vector table address interrupt source vector table address interrupt source vector table address brk instruction 003eh intcm10 001ah operand error 003ch intcm11 001ch nmi 0002h intcm20 001eh intwdt 0004h intcm21 0020h intov0 0006h intcm30 0022h intov1 0008h intcm31 0024h intov4 000ah intcm40 0026h intp0 000ch intcm41 0028h intcc00 intser 002ah intp1 000eh intsr 002ch intcc01 intcsi1 intp2 0010h intst 002eh intcc02 intser2 0030h intp3 0012h intsr2 0032h intcc03 intcsi2 intp4 0014h intst2 0034h intp5 0016h intad 0036h intp6 0018h
pd784044(a), 784046(a) 43 data sheet u13121ej1v1ds 8.3 context switching a specific register bank is selected by hardware when an interrupt request is generated or when the brkcs instruction is executed. execution branches to the vector address stored in advance to the selected register bank, and the current contents of the program counter (pc) and program status word (psw) are stacked to the register bank. the branch destination address must be in a range of 0 to ffffh. figure 8-1. context switching operation when interrupt request is generated v u t w a b r5 r7 d h x c r4 r6 e l vp up register bank n (n = 0 to 7) < 3 > select register bank (rbs0 to rbs2 n) < 4 > rss 0 ie 0 < 6 > exchange < 5 > save < 7 > transfer < 1 > save 0000b < 2 > save (bits 8 through 11 of temporary register) temporary register psw pc19-16 pc15 _ 0 register bank (0 to 7)
pd784044(a), 784046(a) 44 data sheet u13121ej1v1ds 8.4 macro service the pd784046(a) has a total of seven types of macro service. each macro service is outlined below. (1) counter mode: evtcnt operation (a) increments or decrements an 8-bit macro service counter (msc). (b) a vectored interrupt request is generated when the value of msc reaches 0. msc +1 / _ 1 application example: event counter, measurement of number of times of capture (2) block transfer mode: blktrs operation (a) transfers block data between the buffer and an sfr specified by the sfr pointer (sfr.ptr). (b) the transfer source and destination can be an sfr or buffer. the length of the data to be transferred can be byte or word. (c) the number of times data is to be transferred (block size) is specified by msc. (d) msc is auto-decremented ( 1) each time the macro service has been executed. (e) when the value of msc has reached 0, a vectored interrupt request is generated. application example: data transfer/reception of serial interface msc sfr.ptr _ 1 buffer n buffer 1 sfr internal bus
pd784044(a), 784046(a) 45 data sheet u13121ej1v1ds (3) block transfer mode (with memory pointer): blktrs-p operation this is the block transfer mode in (2) with a memory pointer (mem.ptr) appended. the appended buffer area of memp can be freely set on the memory space. remark mem.ptr is auto-incremented (+1: byte data transfer/+2: word data transfer) each time the macro service has been executed. application example: measurement of period and pulse width by capture register of timer 0 msc sfrp _ 1 buffer n buffer 1 sfr internal bus +1 / +2 mem.ptr application example: same as (2) (4) data differential mode: dtadif operation (a) calculates the difference between the contents of the sfr specified by sfr pointer (sfr.ptr) (current value) and the contents of the sfr loaded to the last data buffer (ldb). (b) stores the result of the calculation to a predetermined buffer area. (c) stores the contents of the current value of sfr to ldb. (d) the number of times the data is to be transferred (block size) is specified by msc. the value of msc is auto-decremented ( 1) each time the macro service has been executed. (e) when the value of msc has reached 0, a vectored interrupt request is generated. remark the differential calculation can be performed only an sfr of 16-bit configuration. msc sfr.ptr _ 1 buffer n buffer 1 sfr internal bus differential calculation ldb
pd784044(a), 784046(a) 46 data sheet u13121ej1v1ds (5) data differential mode (with memory pointer): dtadif-p operation this is the data differential mode in (4) with a memory pointer (mem.ptr) appended. the appended mem.ptr can set a buffer area to which the differential data is to be stored on the memory space freely. remarks 1. the differential calculation can be performed only an sfr of 16-bit configuration. 2. the buffer is specified by the result of an operation between mem.ptr and msc note . the value of mem.ptr is not updated after the data has been transferred. note mem.ptr (msc 2) + 2 msc sfr.ptr buffer n buffer 1 ldb _ 1 sfr internal bus differential calculation mem.ptr application example: same as (4) (6) cpu monitoring mode0: sflf0 operation (a) checks the internal operation of the cpu. (b) when the blocks are operating normally, the value given by subtracting 10 from the initial value is transferred to the sfr specified by the sfr pointer (sfr.ptr). application example: used for self checking of the cpu during normal operation. (7) cpu monitoring mode1: self1 operation (a) checks the internal operation of the cpu. (b) when the blocks are operating normally, the value given by subtracting 8 from the initial value is transferred to the sfr specified by the sfr pointer (sfr.ptr). application example: used for self checking of the cpu during normal operation.
pd784044(a), 784046(a) 47 data sheet u13121ej1v1ds 9. local bus interface the pd784046(a) can be connected to an external memory or i/o (memory mapped i/o), supporting a 1m- byte memory space (refer to figure 9-1 ). figure 9-1. example of local bus interface (with external 8-bit bus specified) address bus sram prom character generator data bus ad0-ad7 ad8-ad15 astb lwr rd a16-a19 pd784046(a) latch address bus gate array i/o expansion centronics i/f, etc. decoder
pd784044(a), 784046(a) 48 data sheet u13121ej1v1ds 9.1 memory expansion the external program memory or data memory can be expanded from 256 bytes up to 1m bytes in seven steps. when an external device is connected, the address/data bus and read/write strobe signals are controlled by using ports 4 through 6 and p90 through p93 pins. the functions of these ports and pins are set by the memory expansion mode register (mm). table 9-1. setting of pin function memory expansion pin function mode register port 4 port 5 port 6 mm0-mm3 p40-p47 p50-p57 p60-p63 p90-p93 port mode general-purpose port external memory ad0-ad7 ad8 to ad15 are set stepwise. a16 through a19 are set p90 : rd expansion mode rest of pins can be used as stepwise. p91 : lwr general-purpose port pins. rest of pins can be used as p92 : hwr general-purpose port pins. p93 : astb remark ad8 through ad15 are used as address bus. the number of pins of ports 5 and 6 that are used as address bus pins can be changed according to the size of the external memory connected (external address space), so that the external memory can be expanded stepwise. the pins not used as address bus pins can be used as general-purpose i/o port pins (refer to table 9-2 ). the external address space can be set in seven steps by mm. table 9-2. operations of ports 5 and 6 (in external memory expansion mode) port 5 port 6 external address space p50 p51 p52 p53 p54 p55 p56 p57 p60 p61 p62 p63 general-purpose port 256 bytes or less note ad8 ad9 1k bytes or less note ad10 ad11 4k bytes or less note ad12 ad13 16k bytes or less note ad14 ad15 64k bytes or less a16 a17 256k bytes or less a18 a19 1m bytes or less note when the external 16-bit bus is specified, do not set mm such that the external address space is of this size. caution when the external 16-bit bus is specified, set mm such that all the pins of port 5 (p50 through p57) are used as ad pins (ad8 through ad15).
pd784044(a), 784046(a) 49 data sheet u13121ej1v1ds 9.2 memory space the 1m-byte memory space is divided into the following eight spaces of logical addresses. each space can be controlled by using the programmable wait function and bus sizing function. figure 9-2. memory space 9.3 programmable wait a wait state can be inserted to each of the eight memory spaces while the rd, lwr, and hwr signals are active. even if memories with different access times are connected, therefore, the overall efficiency of the system is not degraded. in addition, an address wait function that extends the active period of the astb signal is also available to extend the address decode time (this function can be set to all the spaces). 9.4 bus sizing function the pd784046(a) can change the external data bus width between 8 and 16 bits when an external device is connected. even if the memory space is divided by eight, the bus width of each memory space can be specified independently. 512k bytes 256k bytes 128k bytes 64k bytes 16k bytes 16k bytes 16k bytes 16k bytes h f f f f f h h 0 f 0 f 0 f 0 f 8 7 h h 0 f 0 f 0 f 0 f 4 3 h h 0 f 0 f 0 f 0 f 2 1 h h 0 f 0 f 0 f 0 f 1 0 h h 0 f 0 f 0 f c b 0 0 h h 0 f 0 f 0 f 8 7 0 0 h h 0 f 0 f 0 f 4 3 0 0 h 0 0 0 0 0
pd784044(a), 784046(a) 50 data sheet u13121ej1v1ds 10. standby function the pd784046(a) has the following standby function modes that reduce the power consumption of the chip. halt mode : this mode stops the operating clock of the cpu. it can reduce the average power consumption through intermittent operation by combination of a normal operation and this mode. idle mode : this mode stops the entire system with the operation of the oscillation circuit continuing. normal program operation can be restored from this mode with the power consumption close to that in the stop mode and time equivalent to that in the halt mode. stop mode : this mode stops the oscillator and stops all the internal operations of the chip to minimize the power consumption to the level of only leakage current. these modes are programmable. macro service can be started from the halt mode. figure 10-1. standby status transition interrupt request note halt setting reset input idle setting nmi reset input macro service request end of first processing end of macro service macro service request end of first processing stop setting reset input nmi o scillation stabilization time expires interrupt request of masked interrupt macro service halt (standby) program operation waits for stabilization of oscillation idle (standby) stop (standby) note only unmasked interrupt request remark only external input of nmi is valid. the watchdog timer cannot be used to release the standby mode (stop/halt/idle).
pd784044(a), 784046(a) 51 data sheet u13121ej1v1ds 11. reset function when a low level is input to the reset pin, the internal hardware is initialized (reset status). when the reset signal goes high, the following data is set to the program counter (pc). lower 8 bits of pc : contents of address 0000h middle 8 bits of pc : contents of address 0001h higher 4 bits of pc : 0 the contents of the pc are assumed as a branch destination address and program execution is started from this address. therefore, the program can be reset and started from any address. set the contents of each register by program as necessary. to prevent malfunctioning due to noise, a noise rejection circuit is provided to the reset input circuit. this noise rejection circuit is a sampling circuit with analog delay. figure 11-1. accepting reset keep the reset signal active until the oscillation stabilization time (about 40 ms) elapses when executing a reset operation on power application or when releasing the stop mode by reset. figure 11-2. reset operation on power application reset (input) internal reset signal delay delay delay pc initialization instruction execution at reset start address reset starts reset ends v dd reset (input) internal reset signal delay initializes pc instruction execution at reset start address oscillation stabilization time reset ends
pd784044(a), 784046(a) 52 data sheet u13121ej1v1ds 12. instruction set (1) 8-bit instructions (( ): combination realized by writing a as r) mov, xch, add, addc, sub, subc, and, or, xor, cmp, mulu, divuw, inc, dec, ror, rol, rorc, rolc, shr, shl, ror4, rol4, dbnz, push, pop, movm, xchm, cmpme, cmpmne, cmpmnc, cmpmc, movbk, xchbk, cmpbke, cmpbkne, cmpbknc, cmpbkc, chkl, chkla table 12-1. instructions for 8-bit addressing 2nd operand #byte a r saddr sfr !addr16 mem r3 [whl+] n none note 2 r saddr !!addr24 [saddrp] pswl [whl ] 1st operand [%saddrg] pswh a (mov) (mov) mov (mov) note 6 mov (mov) mov mov (mov) add note 1 (xch) xch (xch) note 6 (xch) (xch) xch (xch) (add) note 1 (add) note 1 (add) note 1, 6 (add) note 1 add note 1 add note 1 (add) note 1 r mov (mov) mov mov mov mov ror note 3 mulu add note 1 (xch) xch xch xch xch divuw (add) note 1 add note 1 add note 1 add note 1 inc dec saddr mov (mov) note 6 mov mov inc add note 1 (add) note 1 add note 1 xch dec add note 1 dbnz sfr mov mov mov push add note 1 (add) note 1 add note 1 pop chkl chkla !addr16 mov (mov) mov !!addr24 add note 1 mem mov [saddrp] add note 1 [%saddrg] mem3 ror4 rol4 r3 mov mov pswl pswh b, c dbnz stbc, wdm mov [tde+] (mov) movbk note 5 [tde ] (add) note 1 movm note 4 notes 1. addc, sub, subc, and, or, xor, and cmp are the same as add. 2. either the second operand is not used, or the second operand is not an operand address. 3. rol, rorc, rolc, shr, and shl are the same as ror. 4. xchm, cmpme, cmpmne, cmpmnc, and cmpmc are the same as movm. 5. xchbk, cmpbke, cmpbkne, cmpbknc, and cmpbkc are the same as movbk. 6. if saddr is saddr2 in this combination, some instructions have a short code length.
pd784044(a), 784046(a) 53 data sheet u13121ej1v1ds (2) 16-bit instructions (( ): combination realized by writing ax as rp) movw, xchw, addw, subw, cmpw, muluw, mulw, divux, incw, decw, shrw, shlw, push, pop, addwg, subwg, pushu, popu, movtblw, macw, macsw, sacw table 12-2. instructions for 16-bit addressing 2nd operand #word ax rp saddrp sfrp !addr16 mem [whl+] byte n none note 2 rp saddrp !!addr24 [saddrp] 1st operand [%saddrg] ax (movw) (movw) (movw) (movw) note 3 movw (movw) movw (movw) addw note 1 (xchw) (xchw) (xchw) note 3 (xchw) xchw xchw (xchw) (addw) note 1 (addw) note 1 (addw) note 1, 3 (addw) note 1 rp movw (movw) movw movw movw movw shrw mulw note 4 addw note 1 (xchw) xchw xchw xchw shlw incw (addw) note 1 addw note 1 addw note 1 addw note 1 decw saddrp movw (movw) note 3 movw movw incw addw note 1 (addw) note 1 addw note 1 xchw decw addw note 1 sfrp movw movw movw push addw note 1 (addw) note 1 addw note 1 pop !addr16 movw (movw) movw movtblw !!addr24 mem movw [saddrp] [%saddrg] psw push pop sp addwg subwg post push pop pushu popu [tde+] (movw) sacw byte macw macsw notes 1. subw and cmpw are the same as addw. 2. either the second operand is not used, or the second operand is not an operand address. 3. if saddrp is saddrp2 in this combination, some instructions have a short code length. 4. muluw and divux are the same as mulw.
pd784044(a), 784046(a) 54 data sheet u13121ej1v1ds (3) 24-bit instructions (( ): combination realized by writing whl as rg) movg, addg, subg, incg, decg, push, pop table 12-3. instructions for 24-bit addressing 2nd operand #imm24 whl rg saddrg !!addr24 mem1 [%saddrg] sp none note 1st operand rg whl (movg) (movg) (movg) (movg) (movg) movg movg movg (addg) (addg) (addg) addg (subg) (subg) (subg) subg rg movg (movg) movg movg movg incg addg (addg) addg decg subg (subg) subg push pop saddrg (movg) movg !!addr24 (movg) movg mem1 movg [%saddrg] movg sp movg movg incg decg note either the second operand is not used, or the second operand is not an operand address.
pd784044(a), 784046(a) 55 data sheet u13121ej1v1ds (4) bit manipulation instructions mov1, and1, or1, xor1, set1, clr1, not1, bt, bf, bclr, bfset table 12-4. addressing of bit manipulation instructions 2nd operand cy saddr.bit /saddr.bit none note sfr.bit /sfr.bit a.bit /a.bit x.bit /x.bit pswl.bit /pswl.bit pswh.bit /pswh.bit mem2.bit /mem2.bit !addr16.bit /!addr16.bit 1st operand !!addr24.bit /!!addr24.bit cy mov1 and1 not1 and1 or1 set1 or1 clr1 xor1 saddr.bit mov1 not1 sfr.bit set1 a.bit clr1 x.bit bf pswl.bit bt pswh.bit btclr mem2.bit bfset !addr16.bit !!addr24.bit note either the second operand is not used, or the second operand is not an operand address.
pd784044(a), 784046(a) 56 data sheet u13121ej1v1ds (5) call/return/branch instructions call, callf, callt, brk, ret, reti, retb, retcs, retcsb, brkcs, br, bnz, bne, bz, be, bnc, bnl, bc, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, bh, bf, bt, btclr, bfset, dbnz table 12-5. addressing for call/return/branch instructions operand of $addr20 $!addr20 !addr16 !!addr20 rp rg [rp] [rg] !addr11 [addr5] rbn none instruction address basic bc note call call call call call call call callf callt brkcs brk instruction br br br br br br br br ret retcs reti retcsb retb compound bf instruction bt btclr bfset dbnz note bnz, bne, bz, be, bnc, bnl, bl, bnv, bpo, bv, bpe, bp, bn, blt, bge, ble, bgt, bnh, and bh are the same as bc. (6) other instructions adjba, adjbs, cvtbw, location, sel, not, ei, di, swrs
pd784044(a), 784046(a) 57 data sheet u13121ej1v1ds 13. electrical specifications caution the followings are the specifications for the pd784044(a), (a1), and (a2). for the pd784046(a), (a1), and (a2), these are target specifications. (1) electrical specifications of pd784044(a), 784046(a) (1/6) absolute maximum ratings (t a = 25 ?c) parameter symbol conditions ratings unit supply voltage v dd 0.5 to +7.0 v av dd 0.5 to v dd + 0.5 v av ss 0.5 to +0.5 v input voltage v i note 1 0.5 to v dd + 0.5 7.0 v output voltage v o 0.5 to v dd + 0.5 v low-level output current i ol all output pins 15 ma total of all output pins 150 ma high-level output current i oh all output pins 10 ma total of all output pins 100 ma analog input voltage v ian note 2 av dd > v dd 0.5 to v dd + 0.5 v v dd av dd 0.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd 0.5 to v dd + 0.5 v input voltage v dd av dd 0.5 to av dd + 0.5 operating temperature t a 40 to +85 ? c storage temperature t stg 65 to +150 ? c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 25 mhz 40 to +85 ? c 4.5 to 5.5 v capacitance (t a = 25 ?c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o 0 v except measured pins 10 pf i/o capacitance c io 10 pf
pd784044(a), 784046(a) 58 data sheet u13121ej1v1ds (1) electrical specifications of pd784044(a), 784046(a) (2/6) oscillation circuit characteristics (t a = ?0 to +85 ?c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 25 mhz crystal resonator external clock x1 input frequency (f x ) 8 25 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground potential for the capacitor in the oscillation circuit at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not extract any signal from the oscillation circuit. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter
pd784044(a), 784046(a) 59 data sheet u13121ej1v1ds (1) electrical specifications of pd784044(a), 784046(a) (3/6) dc characteristics (t a = 40 to +85 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-level input voltage v il 0 0.8 v high-level input voltage v ih1 note 1 2.2 v dd v v ih2 note 2 0.8 v dd v dd low-level output voltage v ol i ol = 2.0 ma 0.45 v high-level output voltage v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 1 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 25 mhz) 40 70 ma i dd2 halt mode (f xx = 25 mhz) 25 50 ma i dd3 idle mode (f xx = 25 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 215 a v dddr = 5 v 10 % 15 50 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0-p77/ani7, p80/ani8-p87/ani15 used as analog inputs) 4. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 (pins used as analog input, only during the non- sampling operation)
pd784044(a), 784046(a) 60 data sheet u13121ej1v1ds (1) electrical specifications of pd784044(a), 784046(a) (4/6) ac characteristics (t a = 40 to +85 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 80 250 ns address setup time (vs. astb )t sast (0.5 + a) t 20 20 ns address hold time (vs. astb )t hsta 0.5t 20 20 ns astb high-level width t wsth (0.5 + a) t 17 23 ns address rd delay time t dar (1 + a) t 15 65 ns rd address float time t fra 0ns address data input time t daid (2.5 + a + n) t 56 144 ns rd data input time t drid (1.5 + n) t 48 72 ns astb rd delay time t dstr 0.5t 16 24 ns data hold time (vs. rd )t hrid 0ns rd address active time t dra 0.5t 14 26 ns rd low-level width t wrl (1.5 + n) t 30 90 ns address lwr, hwr delay time t daw (1 + a) t 15 65 ns lwr, hwr data output time t dwod 15 ns astb lwr, hwr delay time t dstw 0.5t 16 24 ns data setup time (vs. lwr, hwr )t sodw (1.5 + n) t 25 95 ns data hold time (vs. lwr, hwr )t hwod 0.5t 14 26 ns lwr, hwr astb delay time t dwst 1.5t 15 105 ns lwr, hwr low-level width t wwl (1.5 + n) t 36 84 ns address wait input time t dawt (2 + a) t 50 110 ns astb wait input time t dstwt 1.5t 40 80 ns astb wait hold time t hstwt (1.5 + n) t + 5 125 ns astb wait delay time t dstwth (1.5 + n) t 40 160 note ns rd wait input time t drwt t 40 40 ns rd wait hold time t hrwt (1 + n) t + 5 85 ns rd wait delay time t drwth (1 + n) t 40 120 note ns lwr, hwr wait input time t dwwt t 40 40 ns lwr, hwr wait hold time t hwwt (1 + n) t + 5 85 ns lwr, hwr wait delay time t dwwth (1 + n) t 40 120 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 80 ns.
pd784044(a), 784046(a) 61 data sheet u13121ej1v1ds (1) electrical specifications of pd784044(a), 784046(a) (5/6) serial operation (t a = 40 to +85 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 640 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 280 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 280 ns si1, si2 setup time t sssk 80 ns (vs. sck1, sck2 ) si1, si2 hold time t hssk 80 ns (vs. sck1, sck2 ) sck1, sck2 so1, so2 t dsbsk r = 1 k ? , c = 100 pf 0 150 ns output delay time remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) other operations (t a = 40 to +85 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) ac timing test point v dd 0 v 0.8 v dd or 2.2 v 0.8 v 0.8 v dd or 2.2 v 0.8 v test point
pd784044(a), 784046(a) 62 data sheet u13121ej1v1ds (1) electrical specifications of pd784044(a), 784046(a) (6/6) ad converter characteristics (t a = 40 to +85 ? c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd 0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 4.5 v av ref av dd 0.5 %fsr 3.4 v av ref < 4.5 v 0.7 %fsr quantization error 1/2 lsb conversion time t conv 80 ns t cyk 250 ns 169 t cyk sampling time t samp 80 ns t cyk 250 ns 20 t cyk zero-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb nonlinearity error note 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian 0.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 1.0 3.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 10 a current mode av dddr = 5 v 10% 10 50 a note the quantization error is excluded. remark t cyk = 1/f clk (f clk is internal system clock frequency).
pd784044(a), 784046(a) 63 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (1/6) absolute maximum ratings (t a = 25 ? c) parameter symbol conditions ratings unit supply voltage v dd 0.5 to +7.0 v av dd 0.5 to v dd + 0.5 v av ss 0.5 to +0.5 v input voltage v i note 1 0.5 to v dd + 0.5 7.0 v output voltage v o 0.5 to v dd + 0.5 v low-level output current i ol all output pins 15 ma total of all output pins 150 ma high-level output current i oh all output pins 10 ma total of all output pins 100 ma analog input voltage v ian note 2 av dd > v dd 0.5 to v dd + 0.5 v v dd av dd 0.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd 0.5 to v dd + 0.5 v input voltage v dd av dd 0.5 to av dd + 0.5 operating temperature t a 40 to +110 ? c storage temperature t stg 65 to +150 ? c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 20 mhz 40 to +110 ? c 4.5 to 5.5 v capacitance (t a = 25 ? c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o 0 v except measured pins 10 pf i/o capacitance c io 10 pf
pd784044(a), 784046(a) 64 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (2/6) oscillation circuit characteristics (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 20 mhz crystal resonator external clock x1 input frequency (f x ) 8 20 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground potential for the capacitor in the oscillation circuit at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not extract any signal from the oscillation circuit. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter
pd784044(a), 784046(a) 65 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (3/6) dc characteristics (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-level input voltage v il 0 0.8 v high-level input voltage v ih1 note 1 2.2 v dd v v ih2 note 2 0.8 v dd v dd low-level output voltage v ol i ol = 2.0 ma 0.45 v high-level output voltage v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 2 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 20 mhz) 30 60 ma i dd2 halt mode (f xx = 20 mhz) 15 30 ma i dd3 idle mode (f xx = 20 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 100 a v dddr = 5 v 10 % 15 1000 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0-p77/ani7, p80/ani8-p87/ani15 used as analog inputs) 4. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 (pins used as analog input, only during the non- sampling operation)
pd784044(a), 784046(a) 66 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (4/6) ac characteristics (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 100 250 ns address setup time (vs. astb )t sast (0.5 + a) t 20 30 ns address hold time (vs. astb )t hsta 0.5t 20 30 ns astb high-level width t wsth (0.5 + a) t 17 33 ns address rd delay time t dar (1 + a) t 15 85 ns rd address float time t fra 0ns address data input time t daid (2.5 + a + n) t 56 194 ns rd data input time t drid (1.5 + n) t 53 97 ns astb rd delay time t dstr 0.5t 16 34 ns data hold time (vs. rd )t hrid 0ns rd address active time t dra 0.5t 14 36 ns rd low-level width t wrl (1.5 + n) t 30 120 ns address lwr, hwr delay time t daw (1 + a) t 15 85 ns lwr, hwr data output time t dwod 15 ns astb lwr, hwr delay time t dstw 0.5t 16 34 ns data setup time (vs. lwr, hwr )t sodw (1.5 + n) t 25 125 ns data hold time (vs. lwr, hwr )t hwod 0.5t 14 36 ns lwr, hwr astb delay time t dwst 1.5t 15 135 ns lwr, hwr low-level width t wwl (1.5 + n) t 36 114 ns address wait input time t dawt (2 + a) t 50 150 ns astb wait input time t dstwt 1.5t 40 110 ns astb wait hold time t hstwt (1.5 + n) t + 5 155 ns astb wait delay time t dstwth (1.5 + n) t 40 210 note ns rd wait input time t drwt t 40 60 ns rd wait hold time t hrwt (1 + n) t + 5 105 ns rd wait delay time t drwth (1 + n) t 40 160 note ns lwr, hwr wait input time t dwwt t 40 60 ns lwr, hwr wait hold time t hwwt (1 + n) t + 5 105 ns lwr, hwr wait delay time t dwwth (1 + n) t 40 160 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 100 ns.
pd784044(a), 784046(a) 67 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (5/6) serial operation (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 800 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns si1, si2 setup time t sssk 80 ns (vs. sck1, sck2 ) si1, si2 hold time t hssk 80 ns (vs. sck1, sck2 ) sck1, sck2 so1, so2 t dsbsk r = 1 k ? , c = 100 pf 0 150 ns output delay time remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) other operations (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) ac timing test point v dd 0 v 0.8 v dd or 2.2 v 0.8 v 0.8 v dd or 2.2 v 0.8 v test point
pd784044(a), 784046(a) 68 data sheet u13121ej1v1ds (2) electrical specifications of pd784044(a1), 784046(a1) (6/6) ad converter characteristics (t a = 40 to +110 ? c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd 0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 4.5 v av ref av dd 0.5 %fsr 3.4 v av ref < 4.5 v 0.7 %fsr quantization error 1/2 lsb conversion time t conv 169 t cyk sampling time t samp 20 t cyk zero-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb nonlinearity error note 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian 0.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 3.0 4.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 100 a current mode av dddr = 5 v 10% 10 1000 a note the quantization error is excluded. remark t cyk = 1/f clk (f clk is internal system clock frequency).
pd784044(a), 784046(a) 69 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (1/6) absolute maximum ratings (t a = 25 ? c) parameter symbol conditions ratings unit supply voltage v dd 0.5 to +7.0 v av dd 0.5 to v dd + 0.5 v av ss 0.5 to +0.5 v input voltage v i note 1 0.5 to v dd + 0.5 7.0 v output voltage v o 0.5 to v dd + 0.5 v low-level output current i ol all output pins 15 ma total of all output pins 150 ma high-level output current i oh all output pins 10 ma total of all output pins 100 ma analog input voltage v ian note 2 av dd > v dd 0.5 to v dd + 0.5 v v dd av dd 0.5 to av dd + 0.5 a/d converter reference av ref av dd > v dd 0.5 to v dd + 0.5 v input voltage v dd av dd 0.5 to av dd + 0.5 operating temperature t a 40 to +125 ? c storage temperature t stg 65 to +150 ? c notes 1. pins other than the pins in note 2 . 2. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 caution if any of the parameters exceeds the absolute maximum ratings, even momentarily, the quality of the product may be impaired. the absolute maximum ratings are values that may physically damage the product(s). be sure to use the product(s) within the ratings. recommended operating conditions oscillation frequency t a v dd 8 mhz f xx 20 mhz 40 to +125 ? c 4.5 to 5.5 v capacitance (t a = 25 ? c, v ss = v dd = 0 v) parameter symbol conditions min. typ. max. unit input capacitance c i f = 1 mhz 10 pf output capacitance c o 0 v except measured pins 10 pf i/o capacitance c io 10 pf
pd784044(a), 784046(a) 70 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (2/6) oscillation circuit characteristics (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) resonator recommended circuit item min. max. unit ceramic resonator or oscillation frequency (f xx ) 8 20 mhz crystal resonator external clock x1 input frequency (f x ) 8 20 mhz x1 input rise, fall time 0 5 ns x1 input high-, low-level 20 105 ns width note when the extc bit of the oscillation stabilization time specification register (osts) = 0. input the reverse phase clock of the pin x1 to the pin x2 when the extc bit = 1. caution when using a system clock oscillation circuit, wire the portion enclosed by the dotted line in the diagram above as follows to prevent adverse influence from wiring capacitance: keep the wiring length as short as possible. do not cross the wiring with any other signal lines. do not route the wiring in the vicinity of a line through which a high alternating current flows. always keep the ground potential for the capacitor in the oscillation circuit at the same potential as v ss . do not ground the capacitor to a ground pattern through which a high current flows. do not extract any signal from the oscillation circuit. c1 c2 v ss x1 x2 x1 x2 open note hcmos inverter
pd784044(a), 784046(a) 71 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (3/6) dc characteristics (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. typ. max. unit low-level input voltage v il 0 0.8 v high-level input voltage v ih1 note 1 2.2 v dd v v ih2 note 2 0.8 v dd v dd low-level output voltage v ol i ol = 2.0 ma 0.45 v high-level output voltage v oh i oh = 400 av dd 1.0 v input leakage current i li note 3 0 v v i v dd 10 a analog pin input leakage current i lian note 4 0 v v i av dd 2 a output leakage current i lo 0 v v o v dd 10 a v dd supply current i dd1 operating mode (f xx = 20 mhz) 30 60 ma i dd2 halt mode (f xx = 20 mhz) 15 30 ma i dd3 idle mode (f xx = 20 mhz) 10 20 ma data retention voltage v dddr stop mode 2.5 v data retention current i dddr stop mode v dddr = 2.5 v 2 100 a v dddr = 5 v 10 % 15 1000 a pull-up resistor r l 15 40 80 k ? notes 1. pins other than pins in note 2 . 2. p20/nmi, p21/intp0/to00, p22/intp1/to01, p23/intp2/to02, p24/intp3/to03, p25/intp4, p26/ intp5/ti2, p27/intp6/ti3, p34/asck/sck1, p37/asck2/sck2, x1, x2, reset 3. input and i/o pins (except x1 and x2, and p70/ani0-p77/ani7, p80/ani8-p87/ani15 used as analog inputs) 4. pins p70/ani0-p77/ani7, p80/ani8-p87/ani15 (pins used as analog input, only during the non- sampling operation)
pd784044(a), 784046(a) 72 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (4/6) ac characteristics (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) read/write operation parameter symbol expression min. max. unit system clock cycle time t cyk 100 250 ns address setup time (vs. astb )t sast (0.5 + a) t 20 30 ns address hold time (vs. astb )t hsta 0.5t 20 30 ns astb high-level width t wsth (0.5 + a) t 17 33 ns address rd delay time t dar (1 + a) t 15 85 ns rd address float time t fra 0ns address data input time t daid (2.5 + a + n) t 56 194 ns rd data input time t drid (1.5 + n) t 53 97 ns astb rd delay time t dstr 0.5t 16 34 ns data hold time (vs. rd )t hrid 0ns rd address active time t dra 0.5t 14 36 ns rd low-level width t wrl (1.5 + n) t 30 120 ns address lwr, hwr delay time t daw (1 + a) t 15 85 ns lwr, hwr data output time t dwod 15 ns astb lwr, hwr delay time t dstw 0.5t 16 34 ns data setup time (vs. lwr, hwr )t sodw (1.5 + n) t 25 125 ns data hold time (vs. lwr, hwr )t hwod 0.5t 14 36 ns lwr, hwr astb delay time t dwst 1.5t 15 135 ns lwr, hwr low-level width t wwl (1.5 + n) t 36 114 ns address wait input time t dawt (2 + a) t 50 150 ns astb wait input time t dstwt 1.5t 40 110 ns astb wait hold time t hstwt (1.5 + n) t + 5 155 ns astb wait delay time t dstwth (1.5 + n) t 40 210 note ns rd wait input time t drwt t 40 60 ns rd wait hold time t hrwt (1 + n) t + 5 105 ns rd wait delay time t drwth (1 + n) t 40 160 note ns lwr, hwr wait input time t dwwt t 40 60 ns lwr, hwr wait hold time t hwwt (1 + n) t + 5 105 ns lwr, hwr wait delay time t dwwth (1 + n) t 40 160 note ns note specification when an external wait is inserted remarks 1. t = t cyk = 1/f clk (f clk is internal system clock frequency) 2. a = 1 when an address wait is inserted, otherwise, 0. 3. n indicates the number of the wait cycles by specifying the external wait pins (wait) or program- mable wait control registers 1, 2 (pwc1, pwc2). (n 0. n 1 for t dstwth , t drwth , t dwwth ). 4. calculate values in the expression column with the system clock cycle time to be used because these values depend on the system clock cycle time (t cyk = t). the values in the above expression column are calculated based on t = 100 ns.
pd784044(a), 784046(a) 73 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (5/6) serial operation (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit serial clock cycle time t cysk sck1, sck2 output brg t sft ns sck1, sck2 input external clock 800 ns serial clock low-level width t wskl sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns serial clock high-level width t wskh sck1, sck2 output brg 0.5t sft 40 ns sck1, sck2 input external clock 360 ns si1, si2 setup time t sssk 80 ns (vs. sck1, sck2 ) si1, si2 hold time t hssk 80 ns (vs. sck1, sck2 ) sck1, sck2 so1, so2 t dsbsk r = 1 k ? , c = 100 pf 0 150 ns output delay time remarks 1. t sft is a value set in software. the minimum value is t cyk 8. 2. t cyk = 1/f clk (f clk is internal system clock frequency) other operations (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = 0 v) parameter symbol conditions min. max. unit nmi high, low-level width t wnih , t wnil 10 s intp0-intp6 high, low-level width t with , t witl 4t cysmp ti2, ti3 high, low-level width t wtih , t wtil 4t cysmp reset high, low-level width t wrsh , t wrsl 10 s remarks 1. t cysmp is a sampling clock set in the noise protection control register (npc) in software. when nin = 0, t cysmp = t cyk when nin = 1, t cysmp = t cyk 4 2. t cyk = 1/f clk (f clk is internal system clock frequency) 3. nin: bit n of npc (n = 0-6) ac timing test point v dd 0 v 0.8 v dd or 2.2 v 0.8 v 0.8 v dd or 2.2 v 0.8 v test point
pd784044(a), 784046(a) 74 data sheet u13121ej1v1ds (3) electrical specifications of pd784044(a2), 784046(a2) (6/6) ad converter characteristics (t a = 40 to +125 ? c, v dd = 4.5 to 5.5 v, v ss = av ss = 0 v, v dd 0.5 v av dd v dd ) parameter symbol conditions min. typ. max. unit resolution 10 bit total error note 4.5 v av ref av dd 0.5 %fsr 3.4 v av ref < 4.5 v 0.7 %fsr quantization error 1/2 lsb conversion time t conv 169 t cyk sampling time t samp 20 t cyk zero-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb full-scale error note 4.5 v av ref av dd 1.5 3.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb nonlinearity error note 4.5 v av ref av dd 1.5 2.5 lsb 3.4 v av ref < 4.5 v 1.5 4.5 lsb analog input voltage v ian 0.3 av ref +0.3 v a/d converter reference input av ref 3.4 av dd v voltage av ref current ai ref 3.0 4.0 ma av dd supply current ai dd 2.0 6.0 ma a/d converter data retention ai dddr stop av dddr = 2.5 v 2 100 a current mode av dddr = 5 v 10% 10 1000 a note the quantization error is excluded. remark t cyk = 1/f clk (f clk is internal system clock frequency).
pd784044(a), 784046(a) 75 data sheet u13121ej1v1ds read operation (8 bits) (clk) ad8-ad15 (output) ad0-ad7 (input/output) astb (output) rd (output) wait (input) high-order address high-order address low-order address (output) data (input) low-order address (output) t cyk t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z
pd784044(a), 784046(a) 76 data sheet u13121ej1v1ds write operation (8 bits) (clk) ad8-ad15 (output) ad0-ad7 (output) astb (output) lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl high-order address high-order address low-order address (output) undefined data (output) low-order address (output)
pd784044(a), 784046(a) 77 data sheet u13121ej1v1ds read operation (16 bits) (clk) t cyk address (output) data (input) address (output) t wsth t hsta t dstr t dar t wrl t dstwth t hstwt t dstwt t drwt t dawt t hrwt t drwth t drid t dra t fra t hrid t sast t daid hi-z hi-z hi-z hi-z ad8-ad15 ad0-ad7 (input/output) astb (output) rd (output) wait (input)
pd784044(a), 784046(a) 78 data sheet u13121ej1v1ds write operation (16 bits) (clk) ad8-ad15 ad0-ad7 (output) astb (output) hwr, lwr (output) wait (input) t cyk t dstwth t hstwt t dstwt t dwwt t dawt t hwwt t dwwth t dstw t hsta t wsth t sast t hwod t dwst t dwod t sodw t daw t wwl address (output) data (output) undefined address (output)
pd784044(a), 784046(a) 79 data sheet u13121ej1v1ds serial operation sck1, sck2 so1, so2 si1, si2 t cysk t wskl t dsbsk t sssk t hssk t wskh interrupt input timing t wnih t wnil 0.8 v dd 0.8 v t with t witl 0.8 v dd 0.8 v nmi intp0-intp6 reset input timing t wrsh t wrsl 0.8 v dd 0.8 v reset timer input timing t wtih t wtil 0.8 v dd 0.8 v ti2, ti3
pd784044(a), 784046(a) 80 data sheet u13121ej1v1ds 14. package drawing remark the package dimensions and materials of es versions are the same as those of mass-production versions. 80 pin plastic qfp (14x14) item millimeters inches note each lead centerline is located within 0.13 mm (0.005 inch) of its true position (t.p.) at maximum material condition. l 0.80.2 0.031 +0.009 0.008 m 0.15 0.006 n 0.10 0.004 a 17.20.4 0.6770.016 b 14.00.2 0.551 +0.009 0.008 c 14.00.2 0.551 +0.009 0.008 d 17.20.4 0.6770.016 f 0.825 0.032 g 0.825 0.032 h 0.300.10 0.012 +0.004 0.005 i 0.13 0.005 j 0.65 (t.p.) 0.026 (t.p.) q 0.10.1 0.0040.004 r5 5 5 5 +0.10 0.05 +0.004 0.003 m m l k j h q p n r detail of lead end i g k 1.60.2 0.0630.008 60 61 40 80 1 21 20 41 a b cd f s s80gc-65-3b9-5 s 3.0 max. 0.119 max. p 2.70.1 0.106 +0.005 0.004
pd784044(a), 784046(a) 81 data sheet u13121ej1v1ds 15. recommended soldering conditions these products should be soldered and mounted under the conditions recommended below. for details of soldering conditions, refer to the information document semiconductor device mounting technology manual (c10535e) . for soldering methods and conditions other than those recommended, please contact your nec representa- tive. table 15-1. surface-mount type soldering conditions pd784044gc(a)- -3b9 : 80-pin plastic qfp (14 14 mm) pd784044gc(a1)- -3b9 : 80-pin plastic qfp (14 14 mm) pd784044gc(a2)- -3b9 : 80-pin plastic qfp (14 14 mm) soldering method soldering conditions recommended condition symbol infrared reflow package peak temperature: 235 ? c, time: 30 sec. max. (210 ? c min.), ir35-00-3 number of times: 3 max. partial heating pin temterature: 300 ? c max., 3 sec. max. (per side of device) caution the pd784046(a), (a1), and (a2) are under development. therefore, the soldering conditions for the pd784046(a), (a1), and (a2) are undefined.
pd784044(a), 784046(a) 82 data sheet u13121ej1v1ds appendix a. development tools the following development tools are available for developing systems using the pd784046(a). refer to (5) cautions when the development tools are used. (1) language processing software ra78k4 78k/iv series common assembler package cc78k4 78k/iv series common c compiler package df784046 device file for the pd784046 subseries cc78k4-l 78k/iv series common c compiler library source file (2) flash memory writing tools flashpro ii dedicated flash programmer for microcomputers incorporating flash memory (part number: fl-pr2) fa-80gc adapter for flash memory writing (3) debugging tools when using the ie-78k4-ns in-circuit emulator ie-78k4-ns note 78k/iv series common in-circuit emulator ie-70000-mc-ps-b power supply unit for ie-78k4-ns ie-70000-98-if-c note interface adapter necessary when a pc-9800 series computer (except notebook-type personal computer) is used as host machine ie-70000-cd-if note pc card and interface cable necessary when a pc-9800 series notebook-type personal computer is used as host machine ie-70000-pc-if-c note interface adapter necessary when an ibm pc/at tm or a compatible machine is used as host machine ie-784046-ns-em1 note emulation board for emulating the pd784046 subseries np-80gc emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on the board of the target system for 80-pin plastic qfp (gc-3b9 type) id78k4-ns note integrated debugger for ie-78k4-ns sm78k4 78k/iv series common system simulator df784046 device file for the pd784046 subseries note under development
pd784044(a), 784046(a) 83 data sheet u13121ej1v1ds when using the ie-784000-r in-circuit emulator ie-784000-r 78k/iv series common in-circuit emulator ie-70000-98-if-b interface adapter necessary when a pc-9800 series computer (except notebook-type ie-70000-98-if-c note personal computer) is used as host machine ie-70000-98n-if interface adapter and cable necessary when a pc-9800 series notebook-type personal computer is used as host machine ie-70000-pc-if-b interface adapter necessary when an ibm pc/at or a compatible machine is used ie-70000-pc-if-c note as host machine ie-78000-r-sv3 interface adapter and cable necessary when an ews is used as host machine ie-784000-r-em 78k/iv series common emulation board ie-784046-ns-em1 note emulation board for emulating the pd784046 subseries ie-784046-r-em1 ie78k4-r-ex2 note emulation probe conversion board necessary when the ie-784046-ns-em1 is used in the ie-784000-r. not necessary when the ie-784046-r-em1 is used. ep-78230gc-r emulation probe for 80-pin plastic qfp (gc-3b9 type) ev-9200gc-80 socket to be mounted on the board of the target system made for the 80-pin plastic qfp (gc-3b9 type) id78k4 integrated debugger for ie-784000-r sm78k4 78k/iv series common system simulator df784046 device file for the pd784046 subseries note under development (4) real-time os rx78k/iv real-time os for 78k/iv series mx78k4 os for 78k/iv series
pd784044(a), 784046(a) 84 data sheet u13121ej1v1ds (5) cautions when the development tools are used the id-78k4-ns, id78k4, and sm78k4 are used in combination with the df784046. the cc78k4 and rx78k/iv are used in combination with the ra78k4 and df784046. flashpro ii, fa-80gc, and np-80gc are product of naito densei machida mfg. co., ltd. (tel: (044)822- 3813). contact an nec distributor when purchasing these products. host machines and oss compatible with the software are as follows: host machine [os] pc ews pc-9800 series [windows tm ] hp9000 series 700 tm [hp-ux tm ] ibm pc/at and compatible machines sparcstation tm [sunos tm ] software [japanese/english windows] news tm (risc) [news-os tm ] ra78k4 note cc78k4 note id78k4-ns id78k4 sm78k4 rx78k/iv note mx78k4 note note dos based software
pd784044(a), 784046(a) 85 data sheet u13121ej1v1ds appendix b. related documents device-related documents document name document no. pd784044(a), 784046(a) data sheet this document pd78f4046 preliminary product information u11447e pd784046 subseries user s manual - hardware u11515e 78k/iv series user s manual - instruction u10905e 78k/iv series application note - software basics u10095e development tool-related documents (user s manuals) document name document no. ra78k4 assembler package operation u11334e language u11162e structured assembler preprocessor u11743e cc78k4 c compiler operation u11572e language u11571e ie-78k4-ns u13356e ie-784000-r u12903e ie-784046-ns-em1 u13744e ie-784046-r-em1 u11677e ep-78230 eeu-1515 sm78k4 system simulator windows based reference u10093e sm78k series system simulator external part user open interface u10092e specifications id78k4-ns integrated debugger reference u12796e id78k4 integrated debugger windows based reference u10440e caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of the document when designing your system.
pd784044(a), 784046(a) 86 data sheet u13121ej1v1ds embedded software-related documents (user s manual) document name document no. 78k/iv series real-time os fundamental u10603e installation u10604e 78k/iv series os, mx78k4 fundamental u11779e other documents document name document no. semiconductor selection guide products & packages (cd-rom) x13769e semiconductor device mounting technology manual c10535e quality grades on nec semiconductor devices c11531e nec semiconductor device reliability and quality control c10983e guide to prevent damages for semiconductor devices by c11892e electrostatic discharge (esd) caution the contents of the above related documents are subject to change without notice. be sure to use the latest edition of the document when designing your system.
pd784044(a), 784046(a) 87 data sheet u13121ej1v1ds [memo]
pd784044(a), 784046(a) 88 data sheet u13121ej1v1ds [memo]
pd784044(a), 784046(a) 89 data sheet u13121ej1v1ds notes for cmos devices 1 precaution against esd for semiconductors note: strong electric field, when exposed to a mos device, can cause destruction of the gate oxide and ultimately degrade the device operation. steps must be taken to stop generation of static electricity as much as possible, and quickly dissipate it once, when it has occurred. environmental control must be adequate. when it is dry, humidifier should be used. it is recommended to avoid using insulators that easily build static electricity. semiconductor devices must be stored and transported in an anti-static container, static shielding bag or conductive material. all test and measurement tools including work bench and floor should be grounded. the operator should be grounded using wrist strap. semiconductor devices must not be touched with bare hands. similar precautions need to be taken for pw boards with semiconductor devices on it. 2 handling of unused input pins for cmos note: no connection for cmos device inputs can be cause of malfunction. if no connection is provided to the input pins, it is possible that an internal input level may be generated due to noise, etc., hence causing malfunction. cmos device behave differently than bipolar or nmos devices. input levels of cmos devices must be fixed high or low by using a pull-up or pull-down circuitry. each unused pin should be connected to v dd or gnd with a resistor, if it is considered to have a possibility of being an output pin. all handling related to the unused pins must be judged device by device and related specifications governing the devices. 3 status before initialization of mos devices note: power-on does not necessarily define initial status of mos device. produc- tion process of mos does not define the initial operation status of the device. immediately after the power source is turned on, the devices with reset function have not yet been initialized. hence, power-on does not guarantee out-pin levels, i/o settings or contents of registers. device is not initialized until the reset signal is received. reset operation must be executed imme- diately after power-on for devices having reset function.
pd784044(a), 784046(a) 90 data sheet u13121ej1v1ds regional information some information contained in this document may vary from country to country. before using any nec product in your application, piease contact the nec office in your country to obtain a list of authorized representatives and distributors. they will verify: ? device availability ? ordering information ? product release schedule ? availability of related technical literature ? development environment specifications (for example, specifications for third-party tools and components, host computers, power plugs, ac supply voltages, and so forth) ? network requirements in addition, trademarks, registered trademarks, export restrictions, and other legal issues may also vary from country to country. nec electronics inc. (u.s.) santa clara, california tel: 408-588-6000 800-366-9782 fax: 408-588-6130 800-729-9288 nec electronics (germany) gmbh duesseldorf, germany tel: 0211-65 03 02 fax: 0211-65 03 490 nec electronics (uk) ltd. milton keynes, uk tel: 01908-691-133 fax: 01908-670-290 nec electronics italiana s.r.l. milano, italy tel: 02-66 75 41 fax: 02-66 75 42 99 nec electronics (germany) gmbh benelux office eindhoven, the netherlands tel: 040-2445845 fax: 040-2444580 nec electronics (france) s.a. velizy-villacoublay, france tel: 01-3067-5800 fax: 01-3067-5899 nec electronics (france) s.a. madrid office madrid, spain tel: 091-504-2787 fax: 091-504-2860 nec electronics (germany) gmbh scandinavia office taeby, sweden tel: 08-63 80 820 fax: 08-63 80 388 nec electronics hong kong ltd. hong kong tel: 2886-9318 fax: 2886-9022/9044 nec electronics hong kong ltd. seoul branch seoul, korea tel: 02-528-0303 fax: 02-528-4411 nec electronics singapore pte. ltd. novena square, singapore tel: 253-8311 fax: 250-3583 nec electronics taiwan ltd. taipei, taiwan tel: 02-2719-2377 fax: 02-2719-5951 nec do brasil s.a. electron devices division guarulhos-sp, brasil tel: 11-6462-6810 fax: 11-6462-6829 j01.2
pd784044(a), 784046(a) 91 data sheet u13121ej1v1ds the export of this product from japan is regulated by the japanese government. to export this product may be prohibited without governmental license, the need for which must be judged by the customer. the export or re-export of this product from a country other than japan may also be prohibited without a license from that country. please call an nec sales representative. some of related document may be preliminary, but is not marked as such. please keep this in mind as you refer to this information iebus is a trademark of nec corporation. windows is either a registered trademark or a trademark of microsoft corporation in the united states and/or other countries. pc/at is a trademark of ibm corporation. hp9000 series 700 and hp-ux are trademarks of hewlett-packard company. sparcstation is a trademark of sparc international, inc. sunos is a trademark of sun microsystems inc. news and news-os are trademarks of sony corporation.
pd784044(a), 784046(a) m8e 00. 4 the information in this document is current as of march, 2001. the information is subject to change without notice. for actual design-in, refer to the latest publications of nec's data sheets or data books, etc., for the most up-to-date specifications of nec semiconductor products. not all products and/or types are available in every country. please check with an nec sales representative for availability and additional information. no part of this document may be copied or reproduced in any form or by any means without prior written consent of nec. nec assumes no responsibility for any errors that may appear in this document. nec does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from the use of nec semiconductor products listed in this document or any other liability arising from the use of such products. no license, express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec or others. descriptions of circuits, software and other related information in this document are provided for illustrative purposes in semiconductor product operation and application examples. the incorporation of these circuits, software and information in the design of customer's equipment shall be done under the full responsibility of customer. nec assumes no responsibility for any losses incurred by customers or third parties arising from the use of these circuits, software and information. while nec endeavours to enhance the quality, reliability and safety of nec semiconductor products, customers agree and acknowledge that the possibility of defects thereof cannot be eliminated entirely. to minimize risks of damage to property or injury (including death) to persons arising from defects in nec semiconductor products, customers must incorporate sufficient safety measures in their design, such as redundancy, fire-containment, and anti-failure features. nec semiconductor products are classified into the following three quality grades: "standard", "special" and "specific". the "specific" quality grade applies only to semiconductor products developed based on a customer-designated "quality assurance program" for a specific application. the recommended applications of a semiconductor product depend on its quality grade, as indicated below. customers must check the quality grade of each semiconductor product before using it in a particular application. "standard": computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots "special": transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) "specific": aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems and medical equipment for life support, etc. the quality grade of nec semiconductor products is "standard" unless otherwise expressly specified in nec's data sheets or data books, etc. if customers wish to use nec semiconductor products in applications not intended by nec, they must contact an nec sales representative in advance to determine nec's willingness to support a given application. (note) (1) "nec" as used in this statement means nec corporation and also includes its majority-owned subsidiaries. (2) "nec semiconductor products" means any semiconductor product developed or manufactured by or for nec (as defined above). ? ? ? ? ? ?

▲Up To Search▲

Price & Availability of UPD784046GCA1-XXX-3B9

	To Download UPD784046GCA1-XXX-3B9 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .